利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

182 条记录 (耗时 0.03 秒)

    Memory device and method of fabricating the same
    41.
    发明申请
    Memory device and method of fabricating the same 有权
    存储器件及其制造方法

    公开(公告)号：US20080135912A1

    公开(公告)日：2008-06-12

    申请号：US11976389

    申请日：2007-10-24

    申请人： Chang-Hyun Lee ,  Jung-dal Choi

    发明人： Chang-Hyun Lee ,  Jung-dal Choi

    IPC分类号： H01L29/788 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

    摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

    Method of forming a non-volatile memory device having floating trap type memory cell
    44.
    发明授权
    Method of forming a non-volatile memory device having floating trap type memory cell 失效
    形成具有浮动陷阱型存储单元的非易失性存储器件的方法

    公开(公告)号：US07084030B2

    公开(公告)日：2006-08-01

    申请号：US10632496

    申请日：2003-07-31

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Wang-Chul Shin

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Wang-Chul Shin

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/792

    摘要： A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

    摘要翻译： 非易失性存储器件包括具有电荷存储层的存储器栅极图案的单元区域和具有高电压型栅极图案，低电压型栅极图案和电阻器图案的外围区域。 为了制造上述存储器件，在衬底中形成器件隔离层。 分别在周边区域的低压区域和高压区域形成具有差的厚度的栅极绝缘层。 在周边区域的栅极绝缘层的基本上整个表面上形成第一导电层。 在包括第一导电层的基板的基本上整个表面上顺序地形成包括隧道绝缘层，电荷存储层和阻挡绝缘层和第二导电层的三层。

    Non-volatile memory device and method for fabricating the same
    45.
    发明授权
    Non-volatile memory device and method for fabricating the same 有权

    公开(公告)号：US06818510B2

    公开(公告)日：2004-11-16

    申请号：US10704285

    申请日：2003-11-06

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

    Memory device and method of fabricating the same
    47.
    发明授权
    Memory device and method of fabricating the same 有权
    存储器件及其制造方法

    公开(公告)号：US08334562B2

    公开(公告)日：2012-12-18

    申请号：US12805962

    申请日：2010-08-26

    申请人： Chang-Hyun Lee ,  Jung-dal Choi

    发明人： Chang-Hyun Lee ,  Jung-dal Choi

    IPC分类号： G11C16/04

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

    摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中，它们之间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

    Semiconductor device capable of suppressing short channel effect
    48.
    发明授权
    Semiconductor device capable of suppressing short channel effect 有权
    能够抑制短路效应的半导体装置

    公开(公告)号：US08319268B2

    公开(公告)日：2012-11-27

    申请号：US13239504

    申请日：2011-09-22

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/1083

    摘要： A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.

    摘要翻译： 半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线 其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。

    Methods of operating nonvolatile memory devices to inhibit parasitic charge accumulation therein
    49.
    发明授权
    Methods of operating nonvolatile memory devices to inhibit parasitic charge accumulation therein 有权
    操作非易失性存储器件以抑制其中的寄生电荷累积的方法

    公开(公告)号：US08045385B2

    公开(公告)日：2011-10-25

    申请号：US12956357

    申请日：2010-11-30

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/16

    摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the even-numbered nonvolatile memory cells. This operation to selectively erase the even-numbered nonvolatile memory cells may include erasing the even-numbered nonvolatile memory cells while simultaneously biasing the odd-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the odd-numbered nonvolatile memory cells. The operation to selectively erase the odd-numbered nonvolatile memory cells may include erasing the odd-numbered nonvolatile memory cells while simultaneously biasing the even-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the even-numbered nonvolatile memory cells.

    摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的偶数非易失性存储单元然后选择性地擦除第一串中的奇数非易失性存储单元来擦除第一串非易失性存储单元的操作， 可以与偶数非易失性存储单元进行交织。 选择性地擦除偶数非易失性存储单元的操作可以包括擦除偶数非易失性存储单元，同时在禁止奇数非易失性存储单元擦除的阻塞状态下同时偏置奇数非易失性存储单元。 选择性地擦除奇数非易失性存储单元的操作可以包括擦除奇数非易失性存储单元，同时在阻止偶数非易失性存储单元擦除的阻塞状态下同时偏置偶数非易失性存储单元。