公开(公告)号：US20100327371A1

公开(公告)日：2010-12-30

申请号：US12805962

申请日：2010-08-26

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US20080135912A1

公开(公告)日：2008-06-12

申请号：US11976389

申请日：2007-10-24

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US07808036B2

公开(公告)日：2010-10-05

申请号：US11976389

申请日：2007-10-24

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

公开(公告)号：US08334562B2

公开(公告)日：2012-12-18

申请号：US12805962

申请日：2010-08-26

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中，它们之间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US09564435B2

公开(公告)日：2017-02-07

申请号：US14754400

申请日：2015-06-29

申请人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

发明人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211

摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

摘要翻译： 半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。 逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。 第一和第二栅极电介质层具有不同的厚度。 还讨论了相关设备和制造方法。

公开(公告)号：US20110233636A1

公开(公告)日：2011-09-29

申请号：US13050320

申请日：2011-03-17

申请人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

发明人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.

摘要翻译： 公开了非易失性存储器件和制造非易失性存储器件的方法。 非易失性存储器件包括衬底，衬底上的至少两个栅极结构，以及在至少两个栅极结构之间的衬底的部分中的至少一个杂质区域。 至少一个杂质区域的中心与至少两个栅极结构之间的区域的中心水平偏移。

公开(公告)号：US5877980A

公开(公告)日：1999-03-02

申请号：US824483

申请日：1997-03-26

申请人： Kyong-moo Mang ,  Jung-dal Choi

发明人： Kyong-moo Mang ,  Jung-dal Choi

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.

摘要翻译： 一种在非易失性存储单元上形成导电“程序辅助板”的非易失性存储器件。 对程序辅助板施加适当的电压以大大增加单元耦合比，从而减少编程和擦除电压，并提高操作速度。 制造过程简单，并且其导致更平坦的结构，其有助于后续制造工艺。

公开(公告)号：US5671176A

公开(公告)日：1997-09-23

申请号：US715077

申请日：1996-09-19

申请人： Dong-soo Jang ,  Jung-dal Choi

发明人： Dong-soo Jang ,  Jung-dal Choi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10

摘要： An integrated circuit memory device includes a plurality of wordlines, a plurality of program inhibition lines, a plurality of serially connected memory cell transistors, and a plurality of program inhibition capacitors. Each of the memory cell transistors includes a gate connected to a respective one of the wordlines. Each of the program inhibition capacitors has a first terminal connected to a source/drain of a respective one of the memory cell transistors, and a second terminal connected to a respective one of the program inhibition lines. Related methods are also disclosed.

摘要翻译： 集成电路存储器件包括多个字线，多个编程禁止线，多个串联的存储单元晶体管和多个编程禁止电容器。 每个存储单元晶体管包括连接到字线中相应一个的栅极。 每个编程禁止电容器具有连接到存储单元晶体管的相应一个的源极/漏极的第一端子和连接到相应的一个编程禁止线路的第二端子。 还公开了相关方法。

公开(公告)号：US20160104705A1

公开(公告)日：2016-04-14

申请号：US14754400

申请日：2015-06-29

申请人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

发明人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

IPC分类号： H01L27/088 ,  H01L27/12

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211

摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

摘要翻译： 半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。 逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。 第一和第二栅极电介质层具有不同的厚度。 还讨论了相关设备和制造方法。

公开(公告)号：US08134873B2

公开(公告)日：2012-03-13

申请号：US12591428

申请日：2009-11-19

申请人： Dong-uk Choi ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur ,  Min-tai Yu

发明人： Dong-uk Choi ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur ,  Min-tai Yu

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/10

摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.

摘要翻译： 闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到 第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线， 控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。