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    Method of forming a non-volatile memory device having floating trap type memory cell
    1.
    发明授权
    Method of forming a non-volatile memory device having floating trap type memory cell 失效
    形成具有浮动陷阱型存储单元的非易失性存储器件的方法

    公开(公告)号：US07084030B2

    公开(公告)日：2006-08-01

    申请号：US10632496

    申请日：2003-07-31

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Wang-Chul Shin

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Wang-Chul Shin

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/792

    摘要： A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

    摘要翻译： 非易失性存储器件包括具有电荷存储层的存储器栅极图案的单元区域和具有高电压型栅极图案，低电压型栅极图案和电阻器图案的外围区域。 为了制造上述存储器件，在衬底中形成器件隔离层。 分别在周边区域的低压区域和高压区域形成具有差的厚度的栅极绝缘层。 在周边区域的栅极绝缘层的基本上整个表面上形成第一导电层。 在包括第一导电层的基板的基本上整个表面上顺序地形成包括隧道绝缘层，电荷存储层和阻挡绝缘层和第二导电层的三层。

    Non-volatile memory device with NAND type cell structure
    3.
    发明授权
    Non-volatile memory device with NAND type cell structure 失效
    具有NAND型单元结构的非易失性存储器件

    公开(公告)号：US5936887A

    公开(公告)日：1999-08-10

    申请号：US910025

    申请日：1997-08-12

    申请人： Jung-Dal Choi ,  Dong-Jun Kim ,  Wang-Chul Shin ,  Jong-Han Kim

    发明人： Jung-Dal Choi ,  Dong-Jun Kim ,  Wang-Chul Shin ,  Jong-Han Kim

    IPC分类号： H01L21/8247 ,  G11C11/56 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： H01L27/115 ,  G11C11/5621 ,  G11C16/0483 ,  H01L27/11521 ,  G11C16/24 ,  G11C2211/5649 ,  G11C7/18

    摘要： A non-volatile memory device is disclosed in which a pair of two adjacent memory cell strings are commonly connected to one bit line and the memory cell strings are selectively driven to obtain a relatively wide pitch margin between two bit lines. The device has a conductive plate line which is located along each memory cell string or a pair of memory cell strings to drive memory cells thereof with a relatively low program voltage to a word line. The memory device comprises a plurality of memory cell strings which are arranged in parallel with one another and each of which extends in the same direction as a bit line 12, and a pair of two adjacent memory cell strings 11a and 11b are commonly connected to the bit line 12. The memory device also comprises a string selector for selecting either the first string 11a or the second string 11b in response to signals from string select lines SSL1 and SSL2, and a plurality of plate lines PLa or 21a and PLb or 21b which are respectively arranged on the first and second strings 11a and 11b. In the memory cell, if voltages having different levels are applied to the control gate of a memory cell of the string selected thus and the plate line, at least more than two coupling voltages are induced to a floating gate of a corresponding memory cell so that two bits of information can be stored in and read out of one memory cell. The memory device has a cell structure in which a pair of two adjacent memory cell strings are commonly connected to one bit line, so that margin width between two bit lines, i.e., a bit line pitch can be relatively widely obtained.

    摘要翻译： 公开了一种非易失性存储器件，其中一对两个相邻的存储器单元串共同连接到一个位线，并且存储器单元串被选择性地驱动以在两个位线之间获得相对较宽的间距余量。 该装置具有沿着每个存储单元串或一对存储单元串定位的导电板线，以将具有相对低的编程电压的存储单元驱动到字线。 存储器件包括彼此并联布置的多个存储单元串，并且每个存储单元串沿与位线12相同的方向延伸，并且一对两个相邻的存储单元串11a和11b共同连接到 存储装置还包括用于响应于来自串选择线SSL1和SSL2的信号以及多个板线PLa或21a和PLb或21b而选择第一串11a或第二串11b的串选择器，其中 分别布置在第一和第二弦11a和11b上。 在存储单元中，如果将具有不同电平的电压施加到由此选择的串的存储单元的控制栅极和板线，则至少两个耦合电压被感应到相应存储单元的浮动栅极，使得 两位信息可以存储在一个存储单元中并从其中读出。 存储器件具有单元结构，其中一对两个相邻的存储单元串共同连接到一个位线，使得可以相对广泛地获得两个位线之间的裕度宽度，即位线间距。