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公开(公告)号：US20130084654A1
公开(公告)日：2013-04-04
申请号：US13250960
申请日：2011-09-30
IPC分类号： H01L21/66 , H01L21/3065
CPC分类号： H01L21/31116 , H01L21/02057 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
摘要翻译： 一种形成半导体器件的方法。 提供了具有第一和第二材料的基板，其中第二材料被第一材料遮挡。 使用第一非等离子体蚀刻工艺蚀刻衬底，相对于蚀刻第二材料的速率，蚀刻第一材料的速率更高。 第一非等离子体蚀刻工艺暴露了覆盖第一材料的至少一部分的第二材料。 然后使用包含暴露第一材料的至少一部分的反应性气体的等离子体来蚀刻第二材料。 使用第二非等离子体蚀刻工艺蚀刻包括通过蚀刻第二材料而暴露的第一材料的至少一部分的第一材料。
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公开(公告)号：US20080254612A1
公开(公告)日：2008-10-16
申请号：US12140854
申请日：2008-06-17
申请人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
发明人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76835 , Y10S438/97
摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, O≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.
摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8，O <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。
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公开(公告)号：US07396758B2
公开(公告)日：2008-07-08
申请号：US11619502
申请日：2007-01-03
申请人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
发明人： Elbert E. Huang , Kaushik A. Kumar , Kelly Malone , Dirk Pfeiffer , Muthumanickam Sankarapandian , Christy S. Tyberg
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76835 , Y10S438/97
摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.
摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。
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公开(公告)号：US20130012018A1
公开(公告)日：2013-01-10
申请号：US13614273
申请日：2012-09-13
IPC分类号： H01L21/768
CPC分类号： H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
摘要翻译： 半导体结构制造方法。 提供的结构包括：半导体衬底，半导体衬底上的晶体管，半导体衬底上的N个互连层，以及N层内的临时填充区域。 N至少为2.临时充填区域在足够高的高温下加热，导致临时填充材料被不包括任何固体或液体材料的冷却管道系统所替代。 冷却管系统的第一部分和第二部分分别与第一界面和第二界面处的周围环境直接物理接触，使得垂直于第一界面的第一方向垂直于垂直于第一界面的第二方向 第二个接口 冷却管道系统和环境之间的总体接口包括第一接口和第二接口。
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公开(公告)号：US08298966B2
公开(公告)日：2012-10-30
申请号：US12698370
申请日：2010-02-02
IPC分类号： H01L21/26
CPC分类号： H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.
摘要翻译： 用于形成它的结构和方法。 半导体芯片包括衬底和晶体管。 芯片在衬底上包括N个互连层，N是正整数。 该芯片包括N个互连层内的冷却管道系统。 冷却管系统不包括任何固体或液体材料。 给定冷却管系统中的任何第一点和任何第二点，存在连接第一和第二点并且完全在冷却管系统内的连续路径。 冷却管系统的第一部分与晶体管重叠。 冷却管系统的第二部分高于衬底并且低于顶部互连层。 第二部分与周围环境直接物理接触。
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46.发明申请DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION 审中-公开具有硬掩模保持性的电介质蚀刻工艺的大型接线制造方法公开(公告)号：US20090283912A1
公开(公告)日：2009-11-19
申请号：US12243440
申请日：2008-10-01
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.
摘要翻译： 提供了制造半导体器件的金属布线层的方法，其中镶嵌互连结构形成在BEOL工艺中，其包括电介质帽开放第一工艺以实现硬掩模保持并且控制缓冲氧化物层的气蚀以防止暴露 由缓冲氧化物层保护的底层特征。
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47.发明申请公开(公告)号：US20090107956A1
公开(公告)日：2009-04-30
申请号：US11877965
申请日：2007-10-24
CPC分类号： H01L21/31116 , H01L21/67069 , H01L21/67248 , Y10S438/978
摘要： A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.
摘要翻译： 描述了在半导体晶片内产生温度梯度的技术。 然后采用温度敏感的蚀刻和/或沉积工艺。 这些温度敏感过程在不同温度的区域中以不同的速率进行。 为了减少蚀刻过程中的夹断，选择温度敏感的蚀刻工艺，并且在晶片的表面和次表面之间产生温度梯度，使得蚀刻工艺在表面上比在晶片更深地进行得更慢。 这减少了沟槽开口处的固体反应产物的“结壳”，从而在许多情况下消除了夹断。 可以使用类似的温度敏感的沉积工艺来产生无空隙的高纵横比导体和沟槽填充物。
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48.发明授权Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention 有权具有硬掩模保留的电介质盖蚀刻工艺的大马士革布线制造方法公开(公告)号：US07470616B1
公开(公告)日：2008-12-30
申请号：US12121378
申请日：2008-05-15
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.
摘要翻译： 提供了制造半导体器件的金属布线层的方法，其中镶嵌互连结构形成在BEOL工艺中，其包括电介质帽开放第一工艺以实现硬掩模保持并且控制缓冲氧化物层的气蚀以防止暴露 由缓冲氧化物层保护的底层特征。
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