公开(公告)号：US08037095B2

公开(公告)日：2011-10-11

申请号：US12025864

申请日：2008-02-05

申请人： Welela Haileselassie ,  Lerone W. LaTouche ,  Kelly Malone ,  Lesley W. Mbogo ,  Ugochukwu Nkoku-charles ,  Devon Glenford Williams

发明人： Welela Haileselassie ,  Lerone W. LaTouche ,  Kelly Malone ,  Lesley W. Mbogo ,  Ugochukwu Nkoku-charles ,  Devon Glenford Williams

IPC分类号： G06F17/30

CPC分类号： G06F17/30867 ,  Y10S707/913 ,  Y10S707/914 ,  Y10S707/916 ,  Y10S707/917

摘要： A data accessing method and system. The method includes receiving by a computing system from a first user, a first user profile comprising user preference data associated with the first user. The computing system receives and stores Webcast data associated with a Webcast that has been broadcasted for an entity. The Webcast data comprises audio/video data. The computing system receives from the first user, a first request for access to the first Webcast data. The computing system associates the user preference data with a first set of specified portions of the audio/video data. The computing system retrieves a first portion of audio/video data of the first set of specified portions of the audio/video data. The computing system presents the first portion of audio/video data to the first user.

摘要翻译： 数据访问方法和系统。 该方法包括由计算系统从第一用户接收包括与第一用户相关联的用户偏好数据的第一用户简档。 计算系统接收并存储与为实体广播的网络广播相关联的Webcast数据。 网络广播数据包括音频/视频数据。 计算系统从第一用户接收对第一网络广播数据的访问的第一请求。 计算系统将用户偏好数据与音频/视频数据的指定部分的第一组相关联。 计算系统检索音频/视频数据的第一组指定部分的音频/视频数据的第一部分。 计算系统向第一用户呈现音频/视频数据的第一部分。

公开(公告)号：US07879717B2

公开(公告)日：2011-02-01

申请号：US12140854

申请日：2008-06-17

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/00

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括由具有组成SivNwCxOyHz的聚合物材料构成的掩埋蚀刻停止层，其中0.05和n1E; v和n1E; 0.8,0和n1E; w和n1E;0.9,0.05≤n1E; x和nlE; 0.8,0和nlE; y＆nlE; 0.3,0.05＆ 对于v + w + x + y + z = 1，z＆nlE; 0.8。 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07816253B2

公开(公告)日：2010-10-19

申请号：US11308422

申请日：2006-03-23

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Kelly Malone ,  Sanjay Mehta ,  Terry A. Spooner ,  Chih-Chao Yang

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Kelly Malone ,  Sanjay Mehta ,  Terry A. Spooner ,  Chih-Chao Yang

IPC分类号： H01L21/76 ,  H01L21/425 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831

摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.

摘要翻译： 当在多孔超低k（ULK）材料上构建互连结构时，沟槽和/或通孔的底部通常被以下金属化工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供在层间电介质（ILD）材料上形成互连结构的方法。 该方法包括处理所述ILD材料的暴露区域以产生致密化区域以及金属化所述致密化区域的步骤。

公开(公告)号：US20080315347A1

公开(公告)日：2008-12-25

申请号：US11767789

申请日：2007-06-25

申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  Ronald A. DellaGuardia ,  Qinghuang Lin ,  Kelly Malone ,  Shom S. Ponoth ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  Ronald A. DellaGuardia ,  Qinghuang Lin ,  Kelly Malone ,  Shom S. Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/76 ,  H01L29/00

CPC分类号： H01L21/31695 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing for stress relaxation, hence preventing catastrophic failure of the integrated circuit.

摘要翻译： 使用包括一个或多个间隙或空隙的盖层来制造集成电路。 在对与盖层相邻的层间电介质（ILD）层进行沉积和固化之前，提供间隙或空隙。 间隙或空隙通过允许应力松弛减小并防止拉伸应力累积，从而防止集成电路的灾难性故障。

公开(公告)号：US20080157270A1

公开(公告)日：2008-07-03

申请号：US11618757

申请日：2006-12-30

申请人： Deok-kee Kim ,  Anil K. Chinthakindi ,  Son Van Nguyen ,  Kelly Malone ,  Byeongju Park

发明人： Deok-kee Kim ,  Anil K. Chinthakindi ,  Son Van Nguyen ,  Kelly Malone ,  Byeongju Park

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage. In one embodiment herein the voltage can be supplemented by heating through application of voltage through the first conductor which helps change the resistance of the antifuse element region.

摘要翻译： 本发明的实施例一般涉及熔丝和反熔丝结构，并且包括定位在基板内的铜导体和第一导体上的金属盖。 低k电介质位于基板和金属盖上。 电介质上的氮化钽电阻器，电阻器位于金属帽的上方，使得电介质的反熔丝元件区域位于电阻器和金属帽之间。 电介质的反熔丝元件区域适于通过施加电阻器和铜导体/金属帽之间的电压差来改变电阻值。 在施加电压之后，反熔丝元件区域具有第一高电阻（更紧密地匹配绝缘体）和施加电压之后的第二较低电阻（更接近地匹配导体）。 在本文的一个实施例中，可以通过施加通过第一导体的电压进行加热来补充电压，这有助于改变反熔丝元件区域的电阻。

公开(公告)号：US20070111509A1

公开(公告)日：2007-05-17

申请号：US11619502

申请日：2007-01-03

申请人： Elbert Huang ,  Kaushik Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy Tyberg

发明人： Elbert Huang ,  Kaushik Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07187081B2

公开(公告)日：2007-03-06

申请号：US10699238

申请日：2003-10-31

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L29/40

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US20070048981A1

公开(公告)日：2007-03-01

申请号：US11162219

申请日：2005-09-01

申请人： Griselda Bonilla ,  Richard Conti ,  Timothy Dalton ,  Nicholas Fuller ,  Kelly Malone ,  Satyanarayana Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Richard Conti ,  Timothy Dalton ,  Nicholas Fuller ,  Kelly Malone ,  Satyanarayana Nitta ,  Shom Ponoth

IPC分类号： H01L21/04

CPC分类号： H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/76826

摘要： A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.

摘要翻译： 用于保护半导体器件免受碳耗竭型损伤的方法包括用碳基材料富集多孔层间电介质材料（ILD）的暴露表面，以及对多孔ILD材料实施基于等离子体的操作。 作为基于等离子体的操作的结果，多孔ILD材料的富集减少了碳耗竭的影响。

公开(公告)号：US08647535B2

公开(公告)日：2014-02-11

申请号：US12986266

申请日：2011-01-07

申请人： Kelly Malone ,  Habib Hichri

发明人： Kelly Malone ,  Habib Hichri

IPC分类号： H01B1/02

CPC分类号： H01B5/14 ,  H01B1/02 ,  H01B13/0026 ,  H01L21/283 ,  H01L21/76843 ,  H01L21/76871 ,  Y10T428/24999 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/31663 ,  Y10T428/31678

摘要： A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.

公开(公告)号：US07737561B2

公开(公告)日：2010-06-15

申请号：US11968929

申请日：2008-01-03

申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔线路电平低k电介质层，其上具有金属线导体，其具有底部和侧壁; 在第一多孔线路低k电介质上的抛光停止层; 第二薄的无孔通孔级低k电介质层，用于涂覆和平坦化线和通孔侧壁; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。