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75 条记录 (耗时 0.032 秒)

    Clock data recovery circuit
    42.
    发明授权
    Clock data recovery circuit 失效
    时钟数据恢复电路

    公开(公告)号：US08290107B2

    公开(公告)日：2012-10-16

    申请号：US12320472

    申请日：2009-01-27

    申请人： Masayuki Takase ,  Hideki Endo ,  Koji Fukuda ,  Kenichi Sakamoto

    发明人： Masayuki Takase ,  Hideki Endo ,  Koji Fukuda ,  Kenichi Sakamoto

    IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

    CPC分类号： H04L7/033

    摘要： A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2π. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.

    摘要翻译： 一种时钟数据恢复电路，其分别通过缩短与接收的突发数据信号中包含的抖动分量的每个接收的脉冲数据信号的位同步时间来分别提供稳定的参考时钟，包括产生具有相同时钟的参考时钟的内插器 频率与接收到的突发数据信号的频率相同，并且具有与参考时钟的相位不同的相位的两种类型的确定时钟; 以及可以以M / 2＆amp; pgr为单位改变参考时钟的相位的相位调整控制电路。 在开始接收到脉冲串数据信号之后，时钟数据恢复电路在第一相位调整定时设置较大的相位变化值，并且减小第二次和随后的相位调整定时中的变化值，从而实现与所接收的脉冲串数据的快速位同步 信号产生参考时钟。

    System Apparatus and Method for Interconnecting TDM and Frame/Packet Communication Networks
    43.
    发明申请
    System Apparatus and Method for Interconnecting TDM and Frame/Packet Communication Networks 有权
    用于互连TDM和帧/分组通信网络的系统装置和方法

    公开(公告)号：US20120219006A1

    公开(公告)日：2012-08-30

    申请号：US13465356

    申请日：2012-05-07

    申请人： Masahiko MIZUTANI ,  Yoshihiro Ashi ,  Masayuki Takase ,  Atsushi Iwamura ,  Akihiko Tanaka ,  Hideki Endo ,  Tohru Kazawa

    发明人： Masahiko MIZUTANI ,  Yoshihiro Ashi ,  Masayuki Takase ,  Atsushi Iwamura ,  Akihiko Tanaka ,  Hideki Endo ,  Tohru Kazawa

    IPC分类号： H04L12/56

    CPC分类号： H04L45/04 ,  H04J3/1617 ,  H04J2203/0083

    摘要： An interconnection between fully synchronous networks and next-generation frame communications networks is disclosed. A means of bidirectional frame format conversion between a synchronous multiplexing system and a logical multiplexing system is provided, along with a method of transmitting data between different networks on a path as if it were being transmitted in the same network. Further, when converting network control information in an STM network into data suitable for a packet network, even across the boundary of a synchronous multiplexing system and a logical multiplexing system, a unified communication management means is provided over the whole path.

    摘要翻译： 公开了完全同步网络和下一代帧通信网络之间的互连。 提供了在同步多路复用系统和逻辑多路复用系统之间的双向帧格式转换的方法，以及在路径上的不同网络之间传输数据的方法，如同在同一网络中传输一样。 此外，当将STM网络中的网络控制信息转换为适用于分组网络的数据时，甚至跨越同步复用系统和逻辑多路复用系统的边界，在整个路径上提供统一的通信管理装置。

    Packet communication apparatus with function enhancement module
    44.
    发明授权
    Packet communication apparatus with function enhancement module 有权
    具有功能增强模块的分组通信装置

    公开(公告)号：US07830895B2

    公开(公告)日：2010-11-09

    申请号：US11328106

    申请日：2006-01-10

    申请人： Hideki Endo ,  Kunihiko Toumura ,  Toshiaki Suzuki

    发明人： Hideki Endo ,  Kunihiko Toumura ,  Toshiaki Suzuki

    IPC分类号： H04L12/56

    CPC分类号： H04L67/2814 ,  H04L45/566

    摘要： A packet communication apparatus comprising a node management processor for controlling the whole apparatus, network interfaces for transmitting and receiving packets to and from external networks, function enhancement modules for performing predetermined processes on the packets, and a switch for transferring the packets within the apparatus. The network interface includes a CPU and a memory, the memory stores a program executed by the CPU, the CPU processes the packet received from the external networks by executing the program, and the function enhancement module stores the program stored in the memory.

    摘要翻译： 一种分组通信装置，包括用于控制整个装置的节点管理处理器，用于从外部网络发送和接收分组的网络接口，用于对分组执行预定处理的功能增强模块，以及用于在装置内传送分组的交换机。 网络接口包括CPU和存储器，存储器存储由CPU执行的程序，CPU通过执行程序处理从外部网络接收到的分组，并且功能增强模块存储存储在存储器中的程序。

    TRANSMISSION APPARATUS AND TRANSMISSION SYSTEM
    45.
    发明申请
    TRANSMISSION APPARATUS AND TRANSMISSION SYSTEM 有权
    传输装置和传输系统

    公开(公告)号：US20100135162A1

    公开(公告)日：2010-06-03

    申请号：US12699328

    申请日：2010-02-03

    申请人： Masayuki Takase ,  Hideki Endo ,  Takayuki Kanno ,  Nobuyuki Yamamoto

    发明人： Masayuki Takase ,  Hideki Endo ,  Takayuki Kanno ,  Nobuyuki Yamamoto

    IPC分类号： H04L12/26

    CPC分类号： H04L45/22 ,  H04L45/021 ,  H04L45/04 ,  H04L45/245 ,  H04L45/28 ,  H04L45/50 ,  H04L45/54 ,  H04L47/41 ,  Y02D50/30

    摘要： A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.

    摘要翻译： MPLS OAM的链路聚合功能和维护功能。 相同条目信息存储在执行LA设置的多个电路IF中。 以这种方式，即使使用不同的IF，也可以复用到相同的LSP。 第一个网络IF被假定为OAM ACT，第二个网络IF设置为OAM SBY（SBY）。 OAM帧插入仅由OAM ACT端口执行。 以这种方式，在相反的MPLS传输装置中，可以防止CV帧接收高于指定帧数。 此外，设置交换机转发表将帧从网络侧转发到OAM ACT的第一网络IF。 设置为OAM SBY的第二个网络IF不通过CV接收执行故障检测。 以这种方式，可以防止由于不接收OAM导致的故障的错误检测。

    Transmission apparatus and transmission system
    46.
    发明授权
    Transmission apparatus and transmission system 有权
    传输装置和传输系统

    公开(公告)号：US07675859B2

    公开(公告)日：2010-03-09

    申请号：US11841277

    申请日：2007-08-20

    申请人： Masayuki Takase ,  Hideki Endo ,  Takayuki Kanno ,  Nobuyuki Yamamoto

    发明人： Masayuki Takase ,  Hideki Endo ,  Takayuki Kanno ,  Nobuyuki Yamamoto

    IPC分类号： G08C15/00

    CPC分类号： H04L45/22 ,  H04L45/021 ,  H04L45/04 ,  H04L45/245 ,  H04L45/28 ,  H04L45/50 ,  H04L45/54 ,  H04L47/41 ,  Y02D50/30

    摘要： A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.

    摘要翻译： MPLS OAM的链路聚合功能和维护功能。 相同条目信息存储在执行LA设置的多个电路IF中。 以这种方式，即使使用不同的IF，也可以复用到相同的LSP。 第一个网络IF被假定为OAM ACT，第二个网络IF设置为OAM SBY（SBY）。 OAM帧插入仅由OAM ACT端口执行。 以这种方式，在相反的MPLS传输装置中，可以防止CV帧接收高于指定帧数。 此外，设置交换机转发表将帧从网络侧转发到OAM ACT的第一网络IF。 设置为OAM SBY的第二个网络IF不通过CV接收执行故障检测。 以这种方式，可以防止由于不接收OAM导致的故障的错误检测。

    PON SYSTEM
    47.
    发明申请
    PON SYSTEM 有权
    PON系统

    公开(公告)号：US20100021161A1

    公开(公告)日：2010-01-28

    申请号：US12572695

    申请日：2009-10-02

    申请人： Hideki Endo ,  Masahiko Mizutani ,  Masayuki Takase ,  Kenichi Sakamoto ,  Yoshihiro Ashi ,  Takayuki Kanno ,  Nobuyuki YAMAMOTO

    发明人： Hideki Endo ,  Masahiko Mizutani ,  Masayuki Takase ,  Kenichi Sakamoto ,  Yoshihiro Ashi ,  Takayuki Kanno ,  Nobuyuki YAMAMOTO

    IPC分类号： H04J14/00 ,  H04L12/24

    CPC分类号： H04Q11/0067 ,  H04L47/115 ,  H04L47/263 ,  H04Q11/0071 ,  H04Q2011/0064

    摘要： Disclosed herewith is a PON system and a bandwidth controlling method capable of controlling congestion with use of an upstream bandwidth in a PON section efficiently when congestion occurs in a gateway (GW) connected to an OLT. An OLT connected to a plurality of ONUs through a passive optical network (PON) and to a gateway (GW) through a communication line, when receiving a congestion occurrence notice indicating a congestion occurred output number from a GW, identifies the identifier of the ONU that is using a GW output line having the congestion output port number and shifts the bandwidth controlling of the PON section in a normal mode for allocating a bandwidth to each ONU normally to that in a bandwidth suppression mode for allocating a congestion time allowable bandwidth that is less than the current bandwidth to the ONU having the identified ONU identifier and a bandwidth to each of other ONUs according to its transmission queue length.

    摘要翻译： 这里公开了一种PON系统和带宽控制方法，其能够在连接到OLT的网关（GW）中发生拥塞时有效地控制在PON部分中使用上行带宽的拥塞。 当从GW接收到指示发生拥塞发生拥塞的拥塞发生通知时，通过无线光网络（PON）连接到多个ONU并通过通信线路连接到网关（GW），识别ONU的标识符 正在使用具有拥塞输出端口号的GW输出线，并且以正常模式移动PON部分的带宽控制，以将每个ONU的带宽正常分配给带宽抑制模式中的带宽，以分配拥塞时间允许带宽 小于根据其传输队列长度具有所识别的ONU标识符的ONU的当前带宽和对于每个其他ONU的带宽。