公开(公告)号：US06777322B2

公开(公告)日：2004-08-17

申请号：US10255639

申请日：2002-09-27

申请人： Hyun-dam Jeong ,  Hee-sook Park ,  Hong-jae Shin ,  Byeong-jun Kim

发明人： Hyun-dam Jeong ,  Hee-sook Park ,  Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： H01L214763

CPC分类号： H01L23/53295 ,  C04B35/5603 ,  C04B35/565 ,  H01L21/02137 ,  H01L21/0214 ,  H01L21/02282 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24843 ,  Y10T428/24926 ,  Y10T428/263 ,  Y10T428/31663 ,  H01L2924/00

摘要： A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole—dipole interaction occurs between the first insulating layer and the buffer layer.

摘要翻译： 提供了包括Si-CH 3键的绝缘层的粘合特性的多层电介质层，并且提供了其形成方法。 多层电介质层形成在导电图案上，并且包括由具有包含Si-CH3键的低介电常数的层形成的第一绝缘层。 为了改善第一绝缘层的附着特性，通过用等离子体处理第一绝缘层，在第一绝缘层的表面上形成粘合表面。 或者，通过在第一绝缘层上形成缓冲层，在第一绝缘层和缓冲层之间产生偶极 - 偶极相互作用，来提高第一绝缘层的粘合特性。

公开(公告)号：US06368906B1

公开(公告)日：2002-04-09

申请号：US09209317

申请日：1998-12-09

申请人： Hong-jae Shin ,  Ju-seon Goo

发明人： Hong-jae Shin ,  Ju-seon Goo

IPC分类号： H01L218242

CPC分类号： H01L21/3105 ,  H01L21/31056 ,  H01L21/31111 ,  H01L27/10808 ,  H01L27/10894

摘要： A method for planarizing an interlayer dielectric layer formed on a semiconductor substrate having a step, using wet etch, by depositing first and second layers on the semiconductor substrate and selectively curing the second layer in the lower area using electron beams (E-beams). The second layer, e.g., an SOG layer formed of HSQ, has a lower etch rate during the wet etch in the cured area, to thereby easily planarize the substrate of the interlayer dielectric layer.

摘要翻译： 一种使半导体衬底上形成的层间电介质层平坦化的方法，该层间绝缘层具有通过在半导体衬底上沉积第一层和第二层并使用电子束（E-beam）选择性地固化下部区域中的第二层的步骤。 第二层，例如由HSQ形成的SOG层在固化区域的湿蚀刻期间具有较低的蚀刻速率，从而容易地平坦化层间电介质层的衬底。

公开(公告)号：US06294315B2

公开(公告)日：2001-09-25

申请号：US09765529

申请日：2001-01-19

申请人： Hong-jae Shin ,  Byeong-jun Kim

发明人： Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： G03F726

CPC分类号： H01L21/76835 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829

摘要： A method of forming a metal wiring using a dual damascene process is provided. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.

公开(公告)号：US06218079B1

公开(公告)日：2001-04-17

申请号：US09350806

申请日：1999-07-09

申请人： Hong-jae Shin ,  Byeong-jun Kim

发明人： Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： G03F726

CPC分类号： H01L21/76835 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829

摘要： A method of forming a metal wiring using a dual damascene process is provided. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.

摘要翻译： 提供了一种使用双镶嵌工艺形成金属布线的方法。 使用具有低介电常数的光敏聚合物作为蚀刻掩模。 尽管蚀刻掩模保留在最终结构中，但其低介电常数降低了寄生电容效应。 在该方法中，在第一层间电介质膜上形成具有第一宽度的第一孔的光敏聚合物图案。 在光敏聚合物图案上形成第二层间绝缘膜。 在第二层间电介质膜上形成具有第二孔的第一孔的上方具有大于第一宽度的第二宽度的掩模图案。 通过使用掩模图案作为蚀刻掩模对第二层间电介质膜进行干蚀刻来形成布线区域。 通过使用光敏聚合物图案作为蚀刻掩模对第一层间电介质膜进行干蚀刻来形成通孔区域。