公开(公告)号：US06485815B1

公开(公告)日：2002-11-26

申请号：US09577075

申请日：2000-05-23

申请人： Hyun-dam Jeong ,  Hee-sook Park ,  Hong-jae Shin ,  Byeong-jun Kim

发明人： Hyun-dam Jeong ,  Hee-sook Park ,  Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： B32B2700

CPC分类号： H01L23/53295 ,  C04B35/5603 ,  C04B35/565 ,  H01L21/02137 ,  H01L21/0214 ,  H01L21/02282 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24843 ,  Y10T428/24926 ,  Y10T428/263 ,  Y10T428/31663 ,  H01L2924/00

摘要： A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole-dipole interaction occurs between the first insulating layer and the buffer layer.

摘要翻译： 提供了包括Si-CH 3键的绝缘层的粘合特性的多层电介质层，并且提供了其形成方法。 多层电介质层形成在导电图案上，并且包括由具有包含Si-CH3键的低介电常数的层形成的第一绝缘层。 为了改善第一绝缘层的附着特性，通过用等离子体处理第一绝缘层，在第一绝缘层的表面上形成粘合表面。 或者，通过在第一绝缘层上形成缓冲层，在第一绝缘层和缓冲层之间产生偶极 - 偶极相互作用，来提高第一绝缘层的粘合特性。

公开(公告)号：US06777322B2

公开(公告)日：2004-08-17

申请号：US10255639

申请日：2002-09-27

申请人： Hyun-dam Jeong ,  Hee-sook Park ,  Hong-jae Shin ,  Byeong-jun Kim

发明人： Hyun-dam Jeong ,  Hee-sook Park ,  Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： H01L214763

CPC分类号： H01L23/53295 ,  C04B35/5603 ,  C04B35/565 ,  H01L21/02137 ,  H01L21/0214 ,  H01L21/02282 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24843 ,  Y10T428/24926 ,  Y10T428/263 ,  Y10T428/31663 ,  H01L2924/00

摘要： A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole—dipole interaction occurs between the first insulating layer and the buffer layer.

摘要翻译： 提供了包括Si-CH 3键的绝缘层的粘合特性的多层电介质层，并且提供了其形成方法。 多层电介质层形成在导电图案上，并且包括由具有包含Si-CH3键的低介电常数的层形成的第一绝缘层。 为了改善第一绝缘层的附着特性，通过用等离子体处理第一绝缘层，在第一绝缘层的表面上形成粘合表面。 或者，通过在第一绝缘层上形成缓冲层，在第一绝缘层和缓冲层之间产生偶极 - 偶极相互作用，来提高第一绝缘层的粘合特性。

公开(公告)号：US06294315B2

公开(公告)日：2001-09-25

申请号：US09765529

申请日：2001-01-19

申请人： Hong-jae Shin ,  Byeong-jun Kim

发明人： Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： G03F726

CPC分类号： H01L21/76835 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829

摘要： A method of forming a metal wiring using a dual damascene process is provided. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.

公开(公告)号：US06218079B1

公开(公告)日：2001-04-17

申请号：US09350806

申请日：1999-07-09

申请人： Hong-jae Shin ,  Byeong-jun Kim

发明人： Hong-jae Shin ,  Byeong-jun Kim

IPC分类号： G03F726

CPC分类号： H01L21/76835 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829

摘要： A method of forming a metal wiring using a dual damascene process is provided. A photosensitive polymer having low permittivity is used as an etch mask. Though the etch mask remains in the final structure, its low permittivity reduces parasitic capacitance effects. In this method, a photosensitive polymer pattern having a first hole with a first width is formed on a first interlayer dielectric film. A second interlayer dielectric film is formed on the photosensitive polymer pattern. A mask pattern, having a second hole, above the first hole, with a second width larger than the first width, is formed on the second interlayer dielectric film. A wiring region is formed by dry-etching the second interlayer dielectric film using the mask pattern as an etch mask. A via hole region is formed by dry-etching the first interlayer dielectric film using the photosensitive polymer pattern as an etch mask.

摘要翻译： 提供了一种使用双镶嵌工艺形成金属布线的方法。 使用具有低介电常数的光敏聚合物作为蚀刻掩模。 尽管蚀刻掩模保留在最终结构中，但其低介电常数降低了寄生电容效应。 在该方法中，在第一层间电介质膜上形成具有第一宽度的第一孔的光敏聚合物图案。 在光敏聚合物图案上形成第二层间绝缘膜。 在第二层间电介质膜上形成具有第二孔的第一孔的上方具有大于第一宽度的第二宽度的掩模图案。 通过使用掩模图案作为蚀刻掩模对第二层间电介质膜进行干蚀刻来形成布线区域。 通过使用光敏聚合物图案作为蚀刻掩模对第一层间电介质膜进行干蚀刻来形成通孔区域。

公开(公告)号：US5982039A

公开(公告)日：1999-11-09

申请号：US48391

申请日：1998-03-26

申请人： Woo-sang Jung ,  Gil-heyun Choi ,  Ji-soon Park ,  Byeong-jun Kim

发明人： Woo-sang Jung ,  Gil-heyun Choi ,  Ji-soon Park ,  Byeong-jun Kim

IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole. The method includes forming in an insulator adjacent a contact hole a region of material of a higher thermal conductivity than the insulating layer, depositing a metal in the contact hole and heating the metal, the insulating layer and the region of material of a higher thermal conductivity to flow the metal into the contact hole so as to completely bury the contact hole.

摘要翻译： 公开了一种用于形成完全埋入的接触孔的方法和在互连结构中具有完全埋入的接触孔的半导体器件。 完全埋入的接触孔包括具有形成在其中的接触孔的第一导热性的第一绝缘层。 形成在与接触孔的位置相邻的第一绝缘层中的第二导热材料的区域。 第二热导率大于第一热导率，使得材料区域的热导率大于绝缘层的热导率。 在孔中形成金属，完全埋入接触孔。 该方法包括在绝缘体中邻近形成绝缘层的导热系数较高的材料区域，在接触孔中沉积金属并加热金属，绝缘层和导热系数较高的材料区域 将金属流入接触孔，以完全埋入接触孔。

公开(公告)号：US06355554B1

公开(公告)日：2002-03-12

申请号：US09482584

申请日：2000-01-13

申请人： Gil-heyun Choi ,  Eung-joon Lee ,  Byeong-jun Kim

发明人： Gil-heyun Choi ,  Eung-joon Lee ,  Byeong-jun Kim

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L21/76882

摘要： Methods of fabricating an interconnection to an underlying microelectronic layer include removing a portion of the insulation layer to form a plurality of contact holes having different contact sizes therethrough and thereby expose a portion of the microelectronic layer. A conductive material is deposited on the insulation layer and in the contact hole with a sufficient thickness such that a bridge is generated in the largest contact hole. The deposited conductive material is then reflowed to fill the contact hole and form an interconnection to the underlying microelectronic layer, by supplying a high pressure such that at least the void formed in the largest contact hole is filled. The conductive material may be planarized to thereby expose the insulation layer. The present invention may be applied to an asymmetrical contact hole, for example, a dual damascene structure. In a large contact hole in which it is difficult to bridge the contact hole, a second insulation layer having a lower etch rate is formed on a first insulation layer having a higher etch rate when etched by an etchant. Portions of the first and second insulation layers are then removed to form a contact hole therethrough, leaving portions of the second insulation layer extending the first insulation layer at peripheral portions of the contact hole, overhang the exposed portion of the microelectronic layer.

摘要翻译： 制造与下面的微电子层的互连的方法包括去除绝缘层的一部分以形成通过其中具有不同接触尺寸的多个接触孔，从而暴露微电子层的一部分。 导电材料以足够的厚度沉积在绝缘层和接触孔中，使得在最大接触孔中产生桥。 然后将沉积的导电材料回流以填充接触孔，并通过提供高压使得至少形成在最大接触孔中的空隙被填充而形成与下面的微电子层的互连。 导电材料可以被平坦化，从而暴露绝缘层。 本发明可以应用于非对称接触孔，例如双镶嵌结构。 在其中难以桥接接触孔的大接触孔中，在蚀刻剂蚀刻时，在具有较高蚀刻速率的第一绝缘层上形成具有较低蚀刻速率的第二绝缘层。 然后去除第一和第二绝缘层的部分以形成穿过其中的接触孔，留下第二绝缘层的部分在接触孔的周边部分延伸第一绝缘层，伸出微电子层的暴露部分。

公开(公告)号：US5834847A

公开(公告)日：1998-11-10

申请号：US688606

申请日：1996-07-30

申请人： Woo-sang Jung ,  Gil-heyun Choi ,  Ji-soon Park ,  Byeong-jun Kim

发明人： Woo-sang Jung ,  Gil-heyun Choi ,  Ji-soon Park ,  Byeong-jun Kim

IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole. The method includes forming in an insulator adjacent a contact hole a region of material of a higher thermal conductivity than the insulating layer, depositing a metal in the contact hole and heating the metal, the insulating layer and the region of material of a higher thermal conductivity to flow the metal into the contact hole so as to completely bury the contact hole.

公开(公告)号：US5950105A

公开(公告)日：1999-09-07

申请号：US821067

申请日：1997-03-20

申请人： Woo-sang Jung ,  Gil-heyun Choi ,  Ji-soon Park ,  Byeong-jun Kim

发明人： Woo-sang Jung ,  Gil-heyun Choi ,  Ji-soon Park ,  Byeong-jun Kim

IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method for forming a completely buried contact hole and a semiconductor device having a completely buried contact hole in an interconnection structure is disclosed. The completely buried contact hole includes a first insulating layer of a first thermal conductivity having a contact hole formed therein. A region of material of a second thermal conductivity formed in the first insulating layer adjacent the location of the contact hole. The second thermal conductivity is greater than the first thermal conductivity such that the thermal conductivity of the region of material is greater than the thermal conductivity of the insulating layer. A metal is formed in the hole which completely buries the contact hole. The method includes forming in an insulator adjacent a contact hole a region of material of a higher thermal conductivity than the insulating layer, depositing a metal in the contact hole and heating the metal, the insulating layer and the region of material of a higher thermal conductivity to flow the metal into the contact hole so as to completely bury the contact hole.

摘要翻译： 公开了一种用于形成完全埋入的接触孔的方法和在互连结构中具有完全埋入的接触孔的半导体器件。 完全埋入的接触孔包括具有形成在其中的接触孔的第一导热性的第一绝缘层。 形成在与接触孔的位置相邻的第一绝缘层中的第二导热材料的区域。 第二热导率大于第一热导率，使得材料区域的热导率大于绝缘层的热导率。 在孔中形成金属，完全埋入接触孔。 该方法包括在绝缘体中邻近形成绝缘层的导热系数较高的材料区域，在接触孔中沉积金属并加热金属，绝缘层和导热系数较高的材料区域 将金属流入接触孔，以完全埋入接触孔。