Efficient Parallelized Computation of a BENES Network Configuration

    公开(公告)号:US20220407822A1

    公开(公告)日:2022-12-22

    申请号:US17779157

    申请日:2019-11-28

    Abstract: A routing controller (30) includes an interface (68) and multiple processors (60) The interface is configured to receive a permutation (76) defining requested interconnections between N input ports and N output ports of a Benes network (24). The Benes network includes multiple 2-by-2 switches (42), and is reducible in a plurality of nested subnetworks associated with respective nesting levels, down to irreducible subnetworks including a single 2-by-2 switch. The multiple processors are configured to collectively determine a setting of the 2-by-2 switches that implements the received permutation, including determining sub-settings for two or more subnetworks of a given nesting level in parallel, and to configure the multiple 2-by-2 switches of the Benes network in accordance with the determined setting.

    Adiabatic optical switch using a waveguide on a MEMS cantilever

    公开(公告)号:US20220091341A1

    公开(公告)日:2022-03-24

    申请号:US17421389

    申请日:2019-01-17

    Abstract: An optical switching device (20) includes a substrate (39) and first and second optical waveguides (23, 25) having respective first and second tapered ends (62, 64), which are fixed on the substrate in mutual proximity one to another. A pair of electrodes (36, 38) is disposed on the substrate with a gap therebetween. A cantilever beam (32) is disposed on the substrate within the gap and configured to deflect transversely between first and second positions within the gap in response to a potential applied between the electrodes. A third optical waveguide (21) is mounted on the cantilever beam and has a third tapered end (60) disposed between the first and second tapered ends of the first and second waveguides, so that the third tapered end is in proximity with the first tapered end when the cantilever beam is in the first position and is in proximity with the second tapered end when the cantilever beam is in the second position.

    FAST OPTICAL SWITCH
    44.
    发明申请

    公开(公告)号:US20220029933A1

    公开(公告)日:2022-01-27

    申请号:US16985634

    申请日:2020-08-05

    Abstract: A fast optical switch and networks comprising fast optical switches are disclosed herein. In an example embodiment, a fast optical switch includes two or more fabric switches; a first selector switch; and a second selector switch. The first selector switch may selectively pass a signal to one of the two or more fabric switches. The one of the two or more fabric switches may act on the received signal to provide a switched signal and the second selector switch may selectively receive the switched signal provided by the one of the two or more fabric switches. A slot of the fast optical switch comprises a transmission window of one of the two or more fabric switches that occurs in parallel with at least a portion of a reconfiguration window of the other of the two or more fabric switches.

    Integrated plasmonic modulator
    45.
    发明授权

    公开(公告)号:US12189262B2

    公开(公告)日:2025-01-07

    申请号:US17617603

    申请日:2019-06-10

    Abstract: An optoelectronic device (20) includes thin film structures (56) disposed on a semiconductor substrate (54) and patterned to define components of an integrated drive circuit, which is configured to generate a drive signal. A back end of line (BEOL) stack (42) of alternating metal layers (44, 46) and dielectric layers (50) is disposed over the thin film structures. The metal layers include a modulator layer (48), which contains a plasmonic waveguide (36, 99, 105) and a plurality of electrodes (30, 32, 34, 96, 98, 106), which apply a modulation to surface plasmons polaritons (SPPs) propagating in the plasmonic waveguide in response to the drive signal. A plurality of interconnect layers are patterned to connect the thin film structures to the electrodes. An optical input coupler (38, 82) is configured to couple light into the modulator layer, whereby the light is modulated by the modulation of the SPPs, and an optical output coupler (38, 82) is configured to couple the modulated light out of the modulator layer.

    QUANTUM KEY DISTRIBUTION ENABLED INTRA-DATACENTER NETWORK

    公开(公告)号:US20240214190A1

    公开(公告)日:2024-06-27

    申请号:US18400647

    申请日:2023-12-29

    CPC classification number: H04L9/0852 H04B10/85 H04Q11/0071 H04Q2213/13339

    Abstract: Embodiments are disclosed for a quantum key distribution (QKD) enabled intra-datacenter network. An example system includes a first QKD device and a second QKD device. The first QKD device includes a first quantum-enabled port and a first network port. The second QKD device includes a second quantum-enabled port and a second network port. The first quantum-enabled port of the first QKD device is communicatively coupled to the second quantum-enabled port of the second QKD device via a QKD link associated with quantum communication. Furthermore, the first network port of the first QKD device is communicatively coupled to a first network switch via a first classical link associated with classical network communication. The second network port of the second QKD device is communicatively coupled to a second network switch via a second classical link associated with classical network communication.

    SOFTWARE-DEFINED SIGNAL DEVICE SYSTEMS
    48.
    发明公开

    公开(公告)号:US20240213996A1

    公开(公告)日:2024-06-27

    申请号:US18101675

    申请日:2023-01-26

    CPC classification number: H03M1/124

    Abstract: Embodiments described herein can enable minimum processing performed at a signal device level, such that the majority of the non-domain-specific processing can be offloaded to a processing device. For example, the processing device can receive signal data from a signal device, preprocess the signal data to obtain preprocessed signal data having a data format for domain-specific processing by software executed by at least one processing unit of a processing platform, and provide the preprocessed signal data for domain-specific processing by the software executed by the at least one processing unit.

    Efficient parallelized computation of a Benes network configuration

    公开(公告)号:US12010042B2

    公开(公告)日:2024-06-11

    申请号:US17779157

    申请日:2019-11-28

    CPC classification number: H04L49/254

    Abstract: A routing controller (30) includes an interface (68) and multiple processors (60) The interface is configured to receive a permutation (76) defining requested interconnections between N input ports and N output ports of a Benes network (24). The Benes network includes multiple 2-by-2 switches (42), and is reducible in a plurality of nested subnetworks associated with respective nesting levels, down to irreducible subnetworks including a single 2-by-2 switch. The multiple processors are configured to collectively determine a setting of the 2-by-2 switches that implements the received permutation, including determining sub-settings for two or more subnetworks of a given nesting level in parallel, and to configure the multiple 2-by-2 switches of the Benes network in accordance with the determined setting.

    APPARATUSES AND METHODS FOR REDUCING DATA PORT DELAY

    公开(公告)号:US20240080229A1

    公开(公告)日:2024-03-07

    申请号:US17948717

    申请日:2022-09-20

    CPC classification number: H04L25/03038 H04L2025/03815

    Abstract: Systems, methods, apparatuses, and computer program products for reducing data port downtime are provided. An example network interface device of the present disclosure includes a first data port and a second data port. The network interface device performs a first link training process associated with the first data port coupled to a first communication link to determine a first communication parameter set for the first communication link. The network interface device then deactivates the first data port and performs a second link training process associated the second data port coupled to a second communication link to determine a second communication parameter set. Based on a network usage parameter set associated with a data plane of the network interface device, the network interface device determines whether to activate the first data port concurrently with the second data port.

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