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    MICRO FLUID ACTUATOR
    42.
    发明申请
    MICRO FLUID ACTUATOR 审中-公开

    公开(公告)号：US20200166155A1

    公开(公告)日：2020-05-28

    申请号：US16661060

    申请日：2019-10-23

    Applicant: Microjet Technology Co., Ltd.

    Inventor： Hao-Jan Mou ,  Rong-Ho Yu ,  Cheng-Ming Chang ,  Hsien-Chung Tai ,  Wen-Hsiung Liao ,  Chi-Feng Huang ,  Yung-Lung Han ,  Hsuan-Kai Chen

    IPC: F16K99/00 ,  B81C1/00

    Abstract: A micro fluid actuator includes an orifice layer, a flow channel layer, a substrate, a chamber layer, a vibration layer, a lower electrode layer, a piezoelectric actuation layer and an upper electrode layer, which are stacked sequentially. An outflow aperture, a plurality of first inflow apertures and a second inflow aperture are formed in the substrate by an etching process. A storage chamber is formed in the chamber layer by the etching process. An outflow opening and an inflow opening are formed in the orifice layer by the etching process. An outflow channel, an inflow channel and a plurality of columnar structures are formed in the flow channel layer by a lithography process. By providing driving power which have different phases to the upper electrode layer and the lower electrode layer, the vibration layer is driven to displace in a reciprocating manner, so as to achieve fluid transportation.

    Wafer structure
    44.
    发明授权
    Wafer structure 有权

    公开(公告)号：US11850854B2

    公开(公告)日：2023-12-26

    申请号：US17473276

    申请日：2021-09-13

    Applicant: Microjet Technology Co., Ltd.

    Inventor： Hao-Jan Mou ,  Ying-Lun Chang ,  Hsien-Chung Tai ,  Yung-Lung Han ,  Chi-Feng Huang ,  Wei-Ming Lee

    IPC: B41J2/14

    CPC classification number: B41J2/14145 ,  B41J2/14072 ,  B41J2202/11

    Abstract: A wafer structure is disclosed and includes a chip substrate and an inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the inkjet chip. The inkjet chip includes plural ink-drop generators generated by the semiconductor process on the chip substrate. Each of the plurality of ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and plural horizontal axis array groups having a central stepped pitch equal to or less than 1/600 inches.

    Wafer structure
    46.
    发明授权
    Wafer structure 有权

    公开(公告)号：US11731423B2

    公开(公告)日：2023-08-22

    申请号：US17405874

    申请日：2021-08-18

    Applicant: Microjet Technology Co., Ltd.

    Inventor： Hao-Jan Mou ,  Ying-Lun Chang ,  Hsien-Chung Tai ,  Yung-Lung Han ,  Chi-Feng Huang ,  Chun-Yi Kuo

    IPC: B41J2/14 ,  B41J2/16 ,  H01L29/423 ,  B41J2/045 ,  B41J2/175

    CPC classification number: B41J2/14016 ,  B41J2/1606 ,  H01L29/42372 ,  B41J2/0458 ,  B41J2/1635 ,  B41J2/175 ,  B41J2202/13

    Abstract: A wafer structure is disclosed and includes a chip substrate and plural inkjet chips having plural ink-drip generators. Each ink-drop generator includes a thermal-barrier layer, a resistance heating layer and a protective layer. The thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, a part of the protective layer is formed on the resistance heating layer, and the barrier layer is formed on the protective layer. The ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle. The thermal-barrier layer has a thickness of 500˜5000 angstroms, the protective layer has a thickness of 150˜3500 angstroms, the resistance heating layer has a thickness of 100˜500 angstroms, the resistance heating layer has a length of 5˜30 microns, and the resistance heating layer has a width of 5˜10 microns.

    Wafer structure
    49.
    发明授权
    Wafer structure 有权

    公开(公告)号：US11712890B2

    公开(公告)日：2023-08-01

    申请号：US17116186

    申请日：2020-12-09

    Applicant: Microjet Technology Co., Ltd.

    Inventor： Hao-Jan Mou ,  Ying-Lun Chang ,  Hsien-Chung Tai ,  Chi-Feng Huang ,  Yung-Lung Han ,  Tsung-I Lin

    IPC: B41J2/14 ,  B41J2/16 ,  B41J2/335 ,  B41J2/17

    CPC classification number: B41J2/14024 ,  B41J2/14129 ,  B41J2/14072 ,  B41J2/1707 ,  B41J2/33595 ,  B41J2202/11 ,  B41J2202/13

    Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. Each ink-drop generator includes a barrier layer, an ink-supply chamber and a nozzle. The ink-supply chamber and the nozzle are integrally formed in the barrier layer.

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