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    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    42.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20230055319A1

    公开(公告)日：2023-02-23

    申请号：US17409300

    申请日：2021-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

    IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition. from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

    Integrated circuitry and method used in forming a memory array comprising strings of memory cells
    43.
    发明授权
    Integrated circuitry and method used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11545430B2

    公开(公告)日：2023-01-03

    申请号：US17070269

    申请日：2020-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L29/76 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the conductive first sacrificial material and the conductive second material in the lowest first tier. The conductive first sacrificial material is galvanically etched through the trenches. The lowest second tier is removed after the galvanically etching. After removing the lowest second tier, conducting material is formed in the lowest first tier that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    44.
    发明申请
    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220399357A1

    公开(公告)日：2022-12-15

    申请号：US17348021

    申请日：2021-06-15

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/538 ,  H01L21/768

    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): a hafnium oxide; (b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride in the bilayer being closer to the intervening-material layer than is the silicon dioxide in the bilayer; and (c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy. Methods are disclosed.

    Methods used in forming a memory array comprising strings of memory cells
    46.
    发明授权
    Methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11282847B2

    公开(公告)日：2022-03-22

    申请号：US15931116

    申请日：2020-05-13

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

    Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    47.
    发明申请
    Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220068800A1

    公开(公告)日：2022-03-03

    申请号：US17070269

    申请日：2020-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the conductive first sacrificial material and the conductive second material in the lowest first tier. The conductive first sacrificial material is galvanically etched through the trenches. The lowest second tier is removed after the galvanically etching. After removing the lowest second tier, conducting material is formed in the lowest first tier that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    49.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20210358843A1

    公开(公告)日：2021-11-18

    申请号：US16872691

    申请日：2020-05-12

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11573

    Abstract: Some embodiments include a method in which a first stack of alternating first and second levels is formed. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels and one of the first levels. An etch-stop material and a liner are formed over the stack. A first material is formed over the etch-stop material. Openings are formed to extend through the first material to the etch-stop material. Sacrificial material is formed within the openings. A second stack is formed over the first stack. A second material is formed over the first material. Conductive layers are formed within the first levels. Additional openings are formed to extend to the sacrificial material, and are then extended through the sacrificial material to the conductive layers within the steps. Some embodiments include integrated assemblies.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    50.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20250166704A1

    公开(公告)日：2025-05-22

    申请号：US19027291

    申请日：2025-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

    IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

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