公开(公告)号：US12040253B2

公开(公告)日：2024-07-16

申请号：US17508143

申请日：2021-10-22

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Chet E. Carter ,  Justin D. Shepherdson ,  Collin Howder ,  Joshua Wolanyk

IPC: H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US12029032B2

公开(公告)日：2024-07-02

申请号：US18117989

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11302708B2

公开(公告)日：2022-04-12

申请号：US16674823

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11529 ,  H01L27/1157

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US20210233922A1

公开(公告)日：2021-07-29

申请号：US17229672

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/112 ,  H01L21/67 ,  H01L21/3215 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200058663A1

公开(公告)日：2020-02-20

申请号：US16663068

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11553 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11551

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190221580A1

公开(公告)日：2019-07-18

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/4975

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20190206883A1

公开(公告)日：2019-07-04

申请号：US16270526

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11582

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US09853037B2

公开(公告)日：2017-12-26

申请号：US14949807

申请日：2015-11-23

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have majority carriers of the same conductivity type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20170345910A1

公开(公告)日：2017-11-30

申请号：US15677949

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrey V. Zagrebelny ,  Chet E. Carter ,  Andrew D. Carswell

IPC: H01L29/45 ,  H01L23/532 ,  H01L21/283 ,  H01L21/768 ,  H01L21/321 ,  H01L45/00

Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide. Chemical-mechanical polishing is utilized to form a planarized surface extending across the platinum-containing material and the metal oxide.

公开(公告)号：US20170148802A1

公开(公告)日：2017-05-25

申请号：US14949807

申请日：2015-11-23

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.