公开(公告)号：US11610613B2

公开(公告)日：2023-03-21

申请号：US17212708

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US20230059960A1

公开(公告)日：2023-02-23

申请号：US17894752

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G06F3/06 ,  G06F12/0802

Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

公开(公告)号：US11381432B2

公开(公告)日：2022-07-05

申请号：US17123990

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: H04L27/04 ,  G06F13/38 ,  H04L27/06 ,  H04L27/02 ,  H04L25/49 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US11355169B2

公开(公告)日：2022-06-07

申请号：US16886109

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G06F13/36 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

公开(公告)号：US20210358539A1

公开(公告)日：2021-11-18

申请号：US17387934

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Dean D. Gans ,  Jiyun Li ,  Nathaniel J. Meier ,  Randall J. Rooney

IPC: G11C11/406

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

公开(公告)号：US20210149565A1

公开(公告)日：2021-05-20

申请号：US17033341

申请日：2020-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Shunichi Saito

IPC: G06F3/06 ,  G06F12/10

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks The plurality of memory banks are configured to he arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

公开(公告)号：US11010092B2

公开(公告)日：2021-05-18

申请号：US15975617

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G06F3/06

Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

公开(公告)号：US10978115B2

公开(公告)日：2021-04-13

申请号：US16853917

申请日：2020-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/10

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US10976945B2

公开(公告)日：2021-04-13

申请号：US16048078

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US20200336137A1

公开(公告)日：2020-10-22

申请号：US16917428

申请日：2020-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: H03K5/156 ,  G11C29/50 ,  G11C11/4076 ,  G11C7/22 ,  G11C8/18 ,  G11C7/00

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.