公开(公告)号：US11342042B2

公开(公告)日：2022-05-24

申请号：US16836646

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Yoshinori Fujiwara ,  Kevin G. Werhane

IPC: G11C29/30 ,  G11C29/48 ,  H01L25/065 ,  G11C5/06 ,  H01L23/538 ,  G11C8/06

Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

公开(公告)号：US20220101913A1

公开(公告)日：2022-03-31

申请号：US17545966

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

IPC: G11C11/406 ,  G06F11/30

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

公开(公告)号：US20210304838A1

公开(公告)日：2021-09-30

申请号：US16836646

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Yoshinori Fujiwara ,  Kevin G. Werhane

IPC: G11C29/48 ,  H01L25/065 ,  G11C8/06 ,  H01L23/538 ,  G11C5/06

Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

公开(公告)号：US20210110855A1

公开(公告)日：2021-04-15

申请号：US17131156

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Jung-Hwa Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408

Abstract: An apparatus includes: a master die; one or more slave dies; a ZQ resister between a first node and a second node coupled to a voltage terminal; a ZQ pad coupled to each of the first node of the ZQ resister, the master die and the one or more slave dies; and a calibration channel electrically coupling the master die and the one or more slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the master die and the one or more slave dies.

公开(公告)号：US10410994B2

公开(公告)日：2019-09-10

申请号：US15705867

申请日：2017-09-15

Applicant: Micron Technology, Inc.

Inventor： Kevin Gustav Werhane ,  Jason M. Johnson

IPC: H01L25/065 ,  G01R31/28 ,  G01R31/3177 ,  H03K19/20

Abstract: Techniques for using a single thru-chip signal path to auto-identify and address each integrated circuit within a stack of integrated circuits upon power-up of stack. In an example, each integrated circuit of the stack can include a single auto-identify input terminal, a single auto-identify output terminal, and control logic configured to receive a logic state on the single auto-identify input terminal, to set an internal indicator to one of three states, and to control a state of the single auto-identify output terminal in response to a power up condition or to a change in the logic state of the single auto-identify input terminal.