公开(公告)号：US20200335175A1

公开(公告)日：2020-10-22

申请号：US16388847

申请日：2019-04-18

Applicant: Micron Technology, Inc.

Inventor： Christopher Gordon Wieduwilt ,  Kevin Gustav Werhane

IPC: G11C29/44 ,  G11C29/24

Abstract: A memory device includes a memory bank having multiple addressable groups of memory cells. The multiple addressable groups of memory cells include a primary set of addressable groups and a secondary set of addressable groups. The memory bank has a control circuitry that activates an addressable group with the control circuitry including repair address match circuitry that includes dynamic selection circuitry having multiple first inputs that receive row address values corresponding to the primary set. The dynamic selection circuitry includes one or more second inputs configured to receive one or more fused address values corresponding to the secondary set of addressable groups. The dynamic selection circuitry includes an output configured to selectively transmit a result that is based at least in part on a selection of one or more first inputs and a comparison of the selected one or more first inputs with the one or more the second inputs.

公开(公告)号：US10825544B2

公开(公告)日：2020-11-03

申请号：US16239117

申请日：2019-01-03

Applicant: Micron Technology, Inc.

Inventor： Christopher Gordon Wieduwilt ,  Kevin Gustav Werhane

IPC: G11C29/44 ,  G11C8/12 ,  G11C8/06

Abstract: A memory device includes a memory bank comprising a plurality of addressable groups of memory cells comprising a primary and a secondary set of addressable groups and control circuitry comprising repair address match circuitry, comprising first inputs to receive row address values corresponding to a first group of the primary set of addressable groups, second inputs to receive fused address values corresponding to a second group of the primary set of addressable groups having been repaired, and a selection element, comprising a first selection input to receive a first signal indicative of whether a first row address value is identical to a first fused address value, a second selection input to receive a second signal indicative of whether a second row address value is identical to a second fused address value, and an output to selectively transmit a result as one of the first or second signal.

公开(公告)号：US20200219581A1

公开(公告)日：2020-07-09

申请号：US16239117

申请日：2019-01-03

Applicant: Micron Technology, Inc.

Inventor： Christopher Gordon Wieduwilt ,  Kevin Gustav Werhane

IPC: G11C29/44 ,  G11C8/06 ,  G11C8/12

Abstract: A memory device includes a memory bank comprising a plurality of addressable groups of memory cells comprising a primary and a secondary set of addressable groups and control circuitry comprising repair address match circuitry, comprising first inputs to receive row address values corresponding to a first group of the primary set of addressable groups, second inputs to receive fused address values corresponding to a second group of the primary set of addressable groups having been repaired, and a selection element, comprising a first selection input to receive a first signal indicative of whether a first row address value is identical to a first fused address value, a second selection input to receive a second signal indicative of whether a second row address value is identical to a second fused address value, and an output to selectively transmit a result as one of the first or second signal.

公开(公告)号：US10410994B2

公开(公告)日：2019-09-10

申请号：US15705867

申请日：2017-09-15

Applicant: Micron Technology, Inc.

Inventor： Kevin Gustav Werhane ,  Jason M. Johnson

IPC: H01L25/065 ,  G01R31/28 ,  G01R31/3177 ,  H03K19/20

Abstract: Techniques for using a single thru-chip signal path to auto-identify and address each integrated circuit within a stack of integrated circuits upon power-up of stack. In an example, each integrated circuit of the stack can include a single auto-identify input terminal, a single auto-identify output terminal, and control logic configured to receive a logic state on the single auto-identify input terminal, to set an internal indicator to one of three states, and to control a state of the single auto-identify output terminal in response to a power up condition or to a change in the logic state of the single auto-identify input terminal.

公开(公告)号：US10984884B2

公开(公告)日：2021-04-20

申请号：US16388847

申请日：2019-04-18

Applicant: Micron Technology, Inc.

Inventor： Christopher Gordon Wieduwilt ,  Kevin Gustav Werhane

IPC: G11C29/44 ,  G11C29/24 ,  G11C29/12

Abstract: A memory device includes a memory bank having multiple addressable groups of memory cells. The multiple addressable groups of memory cells include a primary set of addressable groups and a secondary set of addressable groups. The memory bank has a control circuitry that activates an addressable group with the control circuitry including repair address match circuitry that includes dynamic selection circuitry having multiple first inputs that receive row address values corresponding to the primary set. The dynamic selection circuitry includes one or more second inputs configured to receive one or more fused address values corresponding to the secondary set of addressable groups. The dynamic selection circuitry includes an output configured to selectively transmit a result that is based at least in part on a selection of one or more first inputs and a comparison of the selected one or more first inputs with the one or more the second inputs.

公开(公告)号：US20190086469A1

公开(公告)日：2019-03-21

申请号：US15705867

申请日：2017-09-15

Applicant: Micron Technology, Inc.

Inventor： Kevin Gustav Werhane ,  Jason M. Johnson

IPC: G01R31/28 ,  H01L25/065 ,  G01R31/3177

CPC classification number: H01L25/0657 ,  G01R31/2896 ,  G01R31/3177 ,  H01L2225/06544 ,  H03K19/20

Abstract: Techniques for using a single thru-chip signal path to auto-identify and address each integrated circuit within a stack of integrated circuits upon power-up of stack. In an example, each integrated circuit of the stack can include a single auto-identify input terminal, a single auto-identify output terminal, and control logic configured to receive a logic state on the single auto-identify input terminal, to set an internal indicator to one of three states, and to control a state of the single auto-identify output terminal in response to a power up condition or to a change in the logic state of the single auto-identify input terminal;