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公开(公告)号：US11955160B2
公开(公告)日：2024-04-09
申请号：US17846967
申请日：2022-06-22
IPC分类号： H03K5/133 , G11C11/4076 , G11C29/54
CPC分类号： G11C11/4076 , G11C29/54 , H03K5/133
摘要： A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.
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公开(公告)号：US11727967B2
公开(公告)日：2023-08-15
申请号：US17575378
申请日：2022-01-13
发明人： Yoshiro Riho , Hiroshi Akamatsu , Jian Long , Kevin G. Werhane , Liang Liu , Yoshinori Fujiwara
IPC分类号： G11C7/10
CPC分类号： G11C7/1087
摘要： Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.
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公开(公告)号：US20230063588A1
公开(公告)日：2023-03-02
申请号：US17464650
申请日：2021-09-01
发明人： Kevin G. Werhane , Daniel S. Miller
摘要： Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.
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公开(公告)号：US20230420030A1
公开(公告)日：2023-12-28
申请号：US17846967
申请日：2022-06-22
IPC分类号： G11C11/4076 , H03K5/133 , G11C29/54
CPC分类号： G11C11/4076 , H03K5/133 , G11C29/54
摘要： A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.
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公开(公告)号：US20230343376A1
公开(公告)日：2023-10-26
申请号：US18335385
申请日：2023-06-15
发明人： Yoshiro Riho , Hiroshi Akamatsu , Jian Long , Kevin G. Werhane , Liang Liu , Yoshinori Fujiwara
IPC分类号： G11C7/10
CPC分类号： G11C7/1087
摘要： According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.
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公开(公告)号：US10930327B1
公开(公告)日：2021-02-23
申请号：US16773824
申请日：2020-01-27
发明人： Dave Jefferson , C. Omar Benitez , Yoshinori Fujiwara , Christopher S. Wieduwilt , Vivek Kotti , Dennis G. Montierth , Joshua E. Alzheimer , Daniel S. Miller , Kevin G. Werhane , Jason M. Johnson
摘要： Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.
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公开(公告)号：US12079076B2
公开(公告)日：2024-09-03
申请号：US17591362
申请日：2022-02-02
发明人： Yoshinori Fujiwara , Vivek Kotti , Christopher G. Wieduwilt , Jason M. Johnson , Kevin G. Werhane
IPC分类号： G06F11/00 , G06F11/10 , G11C11/408 , G11C11/4096
CPC分类号： G06F11/1068 , G06F11/1032 , G06F11/1044 , G11C11/4085 , G11C11/4087 , G11C11/4096
摘要： Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
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公开(公告)号：US20240241671A1
公开(公告)日：2024-07-18
申请号：US18513438
申请日：2023-11-17
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679
摘要： Methods, apparatuses, and systems related to calibrating memory circuitry according to externally provided reference voltage are described. A memory device may include a calibration control logic that at least isolates an internal reference voltage from an internal buffer. The internal buffer may receive and process the externally provided reference voltage instead of command-address signals for calibration purposes.
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公开(公告)号：US20240071560A1
公开(公告)日：2024-02-29
申请号：US17822032
申请日：2022-08-24
CPC分类号： G11C29/789 , G11C29/4401 , G11C29/46
摘要： An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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公开(公告)号：US11081166B1
公开(公告)日：2021-08-03
申请号：US17000202
申请日：2020-08-21
发明人： Kevin G. Werhane , Jason M. Johnson , Yoshinori Fujiwara , Tyrel Z. Jensen , Daniel S. Miller , David E. Jefferson , Vivek Kotti
IPC分类号： G11C11/408 , G11C11/22
摘要： Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
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