公开(公告)号：US20210304813A1

公开(公告)日：2021-09-30

申请号：US17347957

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Jiyun Li ,  Beau D. Barry ,  Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Michael A. Shore ,  Adam J. Grenzebach ,  Dennis G. Montierth

IPC: G11C11/406 ,  G11C11/408

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

公开(公告)号：US11074964B1

公开(公告)日：2021-07-27

申请号：US16825041

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Jiyun Li

IPC: G11C5/10 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes one or more first equalization transistors proximate the first and second regions, and includes a second equalization transistor proximate the SENSE AMPLIFIER circuitry. Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes an electrical connection coupling the first and second regions to one another.

公开(公告)号：US11069393B2

公开(公告)日：2021-07-20

申请号：US16431641

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Jiyun Li ,  Beau D. Barry ,  Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Michael A. Shore ,  Adam J. Grenzebach ,  Dennis G. Montierth

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

公开(公告)号：US11043500B1

公开(公告)日：2021-06-22

申请号：US16824132

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li

IPC: G11C11/408 ,  H01L27/108 ,  H01L23/528 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a first deck, and having a second deck over the first deck. A first true digit line has a first region along the first deck, and has a second region along the second deck. A first complementary digit line has a first region along the first deck, and has a second region along the second deck. The first true digit line is comparatively compared to the first complementary digit line through SENSE AMPLIFIER circuitry. A second digit line has a first region along the first deck and laterally adjacent the first region of the first complementary digit line, and has a second region along the second deck and laterally adjacent the second region of the first true digit line.

公开(公告)号：US20210057013A1

公开(公告)日：2021-02-25

申请号：US16549942

申请日：2019-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew D. Jenkinson ,  Jiyun Li ,  Dennis G. Montierth ,  Nathaniel J. Meier

IPC: G11C11/408 ,  G06F12/0802 ,  H03K3/03 ,  G11C8/16

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a lust direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).