公开(公告)号：US11189352B2

公开(公告)日：2021-11-30

申请号：US16295845

申请日：2019-03-07

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Larry J. Koudele ,  Michael Sheperek

IPC: G11C16/34 ,  G11C11/56 ,  G11C5/04

Abstract: A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of a memory cell of the memory component. A program targeting operation is performed on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.

公开(公告)号：US20210343353A1

公开(公告)日：2021-11-04

申请号：US17379868

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A method includes determining that a first programming pass of a programming operation has been performed on a memory cell of the memory component, and performing a dynamic program targeting (DPT) operation on the memory cell to calibrate a first program-verify (PV) target value that results in an adjustment to a placement of a first first-pass programming distribution and a second PV target value that results in an adjustment to a placement of a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

公开(公告)号：US20210191617A1

公开(公告)日：2021-06-24

申请号：US16800221

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/26

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

公开(公告)号：US20210117271A1

公开(公告)日：2021-04-22

申请号：US17135645

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Gerald L. Cadloni ,  Bruce A. Liikanen ,  Francis Chew ,  Larry J. Koudele

IPC: G06F11/14 ,  G06F11/10 ,  G11C29/52

Abstract: A memory system is disclosed, including a memory component and a processing device configured to decode one or more codewords saved to a memory region of the memory component, detect that a number of bit errors corresponding to the decoding of the codeword exceeds a correction capability of the processing device, and execute an error recovery routine to reduce the number of detected bit errors to within the correction capability. The error recovery routine can include error recovery operations that are sequentially executed either until the number of bit errors is successfully reduced to within the correction capability or until a set of the error recovery operations has been executed. The error recovery operations can be ordered according to one or more factors, including energy used to execute a respective error recovery operation, a duration of the respective operation, and/or a likelihood of success of the respective operation.

公开(公告)号：US20210042041A1

公开(公告)日：2021-02-11

申请号：US17081901

申请日：2020-10-27

Applicant: Micron Technology, Inc.

Inventor： Larry J. Koudele ,  Bruce A. Liikanen ,  Steve Kientz

IPC: G06F3/06 ,  G11C7/04 ,  G11C16/34 ,  G11C29/02

Abstract: A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.

公开(公告)号：US10885975B2

公开(公告)日：2021-01-05

申请号：US16295829

申请日：2019-03-07

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C11/34 ,  G11C11/56 ,  G11C5/04

Abstract: A processing device determines that read level thresholds between first programming distributions of a second programming pass associated the memory component are calibrated. The processing device changes one or more of the read level thresholds between the first programming distributions. The processing device adjusts one or more read level threshold between second programming distributions of a first programming pass based on the change to the one or more read level thresholds between the first programming distributions.

公开(公告)号：US20200243156A1

公开(公告)日：2020-07-30

申请号：US16848256

申请日：2020-04-14

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C29/50 ,  G11C7/10 ,  H04L1/20 ,  G11C16/34 ,  G11C16/10

Abstract: Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a cRLC operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

公开(公告)号：US20200133528A1

公开(公告)日：2020-04-30

申请号：US16176173

申请日：2018-10-31

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele

IPC: G06F3/06

Abstract: First and second vectors each respectively having first and second magnitudes and first and second phase angles relative to a reference axis are determined by a processing device based on a set of error values corresponding a current processing level for processing data in memory operations on memory cells of a memory component. An estimated processing level offset is generated based on a comparison between at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle. An updated processing level is generated based on the estimated processing level offset, and the updated processing level replaces the current processing level.

公开(公告)号：US20200075120A1

公开(公告)日：2020-03-05

申请号：US16122380

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C29/50 ,  H04L1/20 ,  G11C7/10 ,  G11C16/34 ,  G11C16/10

Abstract: Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a cRLC operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

公开(公告)号：US10566063B2

公开(公告)日：2020-02-18

申请号：US15981810

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steve Kientz

IPC: G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04

Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.