公开(公告)号：US11836377B2

公开(公告)日：2023-12-05

申请号：US17855579

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Abdelhakim Alhussien ,  Ayberk Ozturk ,  Karl D. Schuh ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.

公开(公告)号：US20230297256A1

公开(公告)日：2023-09-21

申请号：US18200685

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Joseph H. Steinmetz ,  Luca Bert ,  William Akin

IPC: G06F3/06 ,  G06F12/0808

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/068 ,  G06F12/0808 ,  G06F3/0644 ,  G06F2212/1044

Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

公开(公告)号：US20230266898A1

公开(公告)日：2023-08-24

申请号：US17680185

申请日：2022-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0683

Abstract: One or more requests are received by a processing device managing one or more memory devices of a memory sub-system from a host system to store a set of data items. A zone group corresponding to a size of the set of data items is identified. A set of zones of the zone group which satisfies a programming parallelism criterion is identified among two or more zones defined in the memory sub-system. The set of data items are programmed to memory cells of the identified set of zones.

公开(公告)号：US20230168997A1

公开(公告)日：2023-06-01

申请号：US18101497

申请日：2023-01-25

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F12/02 ,  G06F12/0844 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F12/0284 ,  G06F12/0844 ,  G06F3/0679 ,  G06F3/0614 ,  G06F3/0647 ,  G06F2212/7207

Abstract: A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

公开(公告)号：US11650881B2

公开(公告)日：2023-05-16

申请号：US17207437

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/10

CPC classification number: G06F11/1428 ,  G06F11/1004 ,  G06F2201/85

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: determining, by a host system, that a failure affects a storage capacity of a memory sub-system, wherein the memory sub-system comprises stored data of a storage structure; instructing, by the host system, the memory sub-system to operate at a reduced capacity and to retain the stored data of the storage structure; receiving, by the host system, a set of storage units of the memory sub-system that are affected by the failure; and recovering, by the host system, data that was in the set of storage units affected by the failure.

公开(公告)号：US11620053B2

公开(公告)日：2023-04-04

申请号：US16663025

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F9/48

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.

公开(公告)号：US20220300372A1

公开(公告)日：2022-09-22

申请号：US17207432

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F11/32 ,  G06F3/06

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.

公开(公告)号：US20220300175A1

公开(公告)日：2022-09-22

申请号：US17207548

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: receiving, by a host system, an indication that a storage capacity of a memory sub-system is affected by a failure, wherein the memory sub-system stores data of a storage structure and comprises memory cells storing multiple bits per cell; instructing, by the host system, the memory sub-system to operate at a reduced capacity, wherein the reduced capacity reduces the quantity of bits stored per memory cell; receiving, by the host system, an indication that the memory sub-system comprises data in excess of the reduced capacity; providing, by the host system, a storage location to the memory sub-system, wherein the storage location is external to the memory sub-system; and enabling the memory sub-system to store the data of the storage structure at the storage location.

公开(公告)号：US20220300174A1

公开(公告)日：2022-09-22

申请号：US17207436

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.

公开(公告)号：US11422745B2

公开(公告)日：2022-08-23

申请号：US16992728

申请日：2020-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F12/10

Abstract: A memory device comprises a first region configured as non-zoned addressable memory and a second region configured as a zone namespace. A write command comprising a payload and a functional designation of the payload is received, wherein the functional description indicates whether the payload comprises sequentially-writable data. Based on the functional designation of the payload, a corresponding one of the first region or the second region of the memory device is determined, wherein the second region is to store sequentially-writable data. The payload is stored in the corresponding one of the first region or the second region of the memory device.