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41.发明申请公开(公告)号：US20210400286A1
公开(公告)日：2021-12-23
申请号：US16906261
申请日：2020-06-19
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale
Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, a data storage device may be configured to execute instructions with matrix operands and configured with: an interface to receive a video stream; and random access memory to buffer a portion of the video stream as an input to an Artificial Neural Network and to store instructions executable by the Deep Learning Accelerator and matrices of the Artificial Neural Network. The Deep Learning Accelerator can execute the instructions to generate an output of the Artificial Neural Network, including analytics of the buffer portion. A video encoder in the data storage device may use the analytics to compress the portion of the video stream for storing in the device.
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公开(公告)号：US20210397771A1
公开(公告)日：2021-12-23
申请号：US16906213
申请日：2020-06-19
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale
Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated sensor device may be configured to execute instructions with matrix operands and configured with: a sensor to generate measurements of stimuli; random access memory to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a host interface connectable to a host system; and a controller to store the measurements generated by the sensor into the random access memory as an input to the Artificial Neural Network. After the Deep Learning Accelerator generates in the random access memory an output of the Artificial Neural Network by executing the instructions to process the input, the controller may communicate the output to a host system through the host interface.
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公开(公告)号：US20210319823A1
公开(公告)日：2021-10-14
申请号：US16844997
申请日：2020-04-09
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Jaime Cummins
Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.
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公开(公告)号：US20210319821A1
公开(公告)日：2021-10-14
申请号：US16844988
申请日：2020-04-09
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Jaime Cummins
Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to perform at least computations on matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; and an interface to a memory controller. The interface may be configured to facilitate access to the random access memory by the memory controller. In response to an indication provided in the random access memory, the Deep Learning Accelerator may execute the instructions to apply input that is stored in the random access memory to the Artificial Neural Network, generate output from the Artificial Neural Network, and store the output in the random access memory.
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公开(公告)号：US11120805B1
公开(公告)日：2021-09-14
申请号：US16906230
申请日：2020-06-19
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale
IPC: G10L15/00 , G10L15/16 , G10L17/18 , G06F17/16 , G06N3/08 , G06N3/10 , G10L25/63 , H04R17/02 , H04R1/04 , G10L17/04 , H04R3/00 , G10L25/30 , G10L17/00
Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, a microphone may be configured to execute instructions with matrix operands and configured with: a transducer to convert sound waves to electrical signals; an analog to digital converter to generate audio data according to the electrical signals; random access memory to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; and a controller to store the audio data in the random access memory as an input to the Artificial Neural Network. The Deep Learning Accelerator can execute the instructions to generate an output of the Artificial Neural Network, which may be provided as the primary output of the microphone to a computer system, such as a voice-based digital assistant.
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Patent Agency Ranking
公开(公告)号：US20210271622A1
公开(公告)日：2021-09-02
申请号：US17326141
申请日：2021-05-20
Applicant: Micron Technology, Inc.
Inventor： Christopher Joseph Bueb , Poorna Kale
Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.
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公开(公告)号：US20210256349A1
公开(公告)日：2021-08-19
申请号：US16791851
申请日：2020-02-14
Applicant: Micron Technology, Inc.
Inventor： Robert Richard Noel Bielby , Poorna Kale
Abstract: Systems, methods and apparatuses to control quality of service of a data storage device. For example, the data storage device receives an input data stream and provides an output data stream. Based at least in part on the input data stream and/or the output data stream, the data storage device determines a quality of service configuration using an artificial neural network. A controller of the data storage device uses the quality of service configuration to control operations of the data storage device that are relevant to quality of service of the data storage device. For example, the configuration identifies optimized strategies and parameters of caching or buffering, and optimized timing and frequency of background maintenance processes, such as garbage collection, wear leveling, etc.
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公开(公告)号：US11093766B1
公开(公告)日：2021-08-17
申请号：US16840244
申请日：2020-04-03
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Robert Richard Noel Bielby
Abstract: Systems, methods and apparatuses to detect an item left in a vehicle and to generate an alert about the item. For example, a camera configured in a vehicle can be used to monitor an item associated with a user of the vehicle. The item as in an image from the camera can be identified and recognized using an artificial neural network. In response to a determination that the item recognized in the image is left in the vehicle after the user has exited the vehicle, an alert is generated to indicate that an item is in the vehicle but the user is leaving the vehicle.
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公开(公告)号：US20210208984A1
公开(公告)日：2021-07-08
申请号：US17301098
申请日：2021-03-24
Applicant: Micron Technology, Inc.
Inventor： Christopher J. Bueb , Poorna Kale
IPC: G06F11/16 , G06F11/30 , G06F11/07 , G11C11/408 , G11C11/409 , G11C29/52 , G06F12/02
Abstract: Disclosed is a system comprising a memory component and a processing device operatively coupled with the memory component, to provide, to a host system, geometric parameters of the memory component, receive, from the host system, a first data to be stored in the memory component, execute a first write operation to program the first data into the memory component, detect that the first write operation has failed, provide a failure notification to the host system, wherein the failure notification comprises an indication of a range of memory cells storing, after the first write operation, incorrect data, and receive, from the host system, a second data to be stored in the memory component, in response to the host system identifying, based on the geometric parameters and the failure notification, a range of logical addresses of the memory component corresponding to the range of memory cells storing incorrect data
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公开(公告)号：US20210173577A1
公开(公告)日：2021-06-10
申请号：US16705606
申请日：2019-12-06
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale
Abstract: One or more parameters indicative of a request to segment the memory device into multiple partitions for use by a host system are received. Responsive to receiving the one or more parameters indicative of the request to segment the memory device into multiple partitions, a first partition is configured with one or more configuration settings based on the one or more parameters. Configuring the first partition includes determining a memory type from multiple memory types based on the one or more parameters, and configuring the first partition to operate as the determined memory type. The memory types define a number of bits that a memory cell of the first partition is to store.
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