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    Pixel calculating device
    41.
    发明授权
    Pixel calculating device 有权
    像素计算装置

    公开(公告)号：US06809777B2

    公开(公告)日：2004-10-26

    申请号：US10019419

    申请日：2001-12-18

    申请人： Hiroyuki Oka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara ,  Makoto Hirai ,  Kozo Kimura ,  Ryuji Matsuura ,  Hiroyuki Morishita ,  Toshiaki Tsuji

    发明人： Hiroyuki Oka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara ,  Makoto Hirai ,  Kozo Kimura ,  Ryuji Matsuura ,  Hiroyuki Morishita ,  Toshiaki Tsuji

    IPC分类号： H04N964

    CPC分类号： H04N19/80 ,  G06T1/20 ,  G06T5/20

    摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

    摘要翻译： 用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。 每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。 使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。 通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

    Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
    42.
    发明授权
    Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream 失效
    多线程处理器，用于通过灵活地控制每个指令流中的吞吐量来彼此独立地处理多个指令流

    公开(公告)号：US6105127A

    公开(公告)日：2000-08-15

    申请号：US920135

    申请日：1997-08-27

    申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Kousuke Yoshioka

    发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Kousuke Yoshioka

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48

    CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3822 ,  G06F9/3851

    摘要： A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit; a holding unit for holding the priority level of each instruction stream; and a control unit for deciding which decoded instruction should be issued to a functional unit designated by two or more instruction issue requests at the same time, in accordance with the priority levels held by the holding unit.

    摘要翻译： 提供了一种用于执行多个指令流的多线程处理器。 该多线程处理器包括：用于执行指令的多个功能单元; 多个指令解码单元，一对一地对应于多个指令流，用于分别解码指令，并产生指令发出请求，用于指定应该向哪个功能单元发出解码指令，并请求为 向指定的功能单元发出解码指令; 保持单元，用于保持每个指令流的优先级; 以及控制单元，用于根据由保持单元保持的优先级，同时根据由两个或多个指令发出请求指定的功能单元来决定哪个解码指令被发出。

    Processing system for branch instruction
    43.
    发明授权
    Processing system for branch instruction 失效
    分支指令处理系统

    公开(公告)号：US5197136A

    公开(公告)日：1993-03-23

    申请号：US614680

    申请日：1990-11-19

    申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Toshimichi Matsuzaki

    发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Toshimichi Matsuzaki

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804

    摘要： A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. The commands are sequentially transferred from the decoder to an execution unit. The execution unit sequentially executes the transferred commands. The decoder serves to detect the branch instruction. When the branch instruction is detected, a normal instruction fetching process is interrupted and the branch destination instruction is promptly fetched to the decoder. The decoder prevents a command of the branch instruction from being transferred to the execution unit.

    摘要翻译： 存储器保存包括分支指令和相应的分支目的地指令的指令。 这些指令从存储器顺序取出到解码器。 解码器顺序地对获取的指令进行解码并从相应的指令导出命令。 这些命令从解码器顺序传送到执行单元。 执行单元依次执行传送命令。 解码器用于检测分支指令。 当检测到分支指令时，正常指令取出处理被中断，并且分支目的地指令被迅速地提取到解码器。 解码器防止转移指令的命令被传送到执行单元。

    Integrated circuit for video/audio processing
    44.
    发明授权
    Integrated circuit for video/audio processing 有权
    用于视频/音频处理的集成电路

    公开(公告)号：US08811470B2

    公开(公告)日：2014-08-19

    申请号：US10599494

    申请日：2005-04-01

    申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    IPC分类号： H04N7/12

    CPC分类号： G06F13/4027 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042

    摘要： An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

    摘要翻译： 用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。 集成电路包括微型计算机，其包括CPU，用于向外部设备输入/输出视频和音频流的流输入/输出，执行媒体处理的媒体处理器，该媒体处理包括至少一个压缩和解压缩视频，以及 输入到流输入/输出的音频流，将由媒体处理器进行媒体处理的视频和音频流转换成视频和音频信号并将这些信号输出到外部设备的AV输入/输出。 存储器接口控制微机，流输入/输出，媒体处理器和AV输入/输出之间的数据传输以及外部存储器。

    INTEGRATED CIRCUIT MANUFACTURING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
    45.
    发明申请
    INTEGRATED CIRCUIT MANUFACTURING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    集成电路制造方法和半导体集成电路

    公开(公告)号：US20120110535A1

    公开(公告)日：2012-05-03

    申请号：US13383335

    申请日：2011-05-27

    申请人： Daisuke Iwahashi ,  Masayoshi Tojima ,  Tokuzo Kiyohara

    发明人： Daisuke Iwahashi ,  Masayoshi Tojima ,  Tokuzo Kiyohara

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0207

    摘要： In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus.

    摘要翻译： 在半导体集成电路制造方法的布局设计步骤中，当发现在外部端子与外部端子对应的IO块（外部端子I / F电路）之间的布线长度在包括 功能块和IO块被确定，IO块的放置被确定为使得IO块靠近外部端子放置以减轻对IO块和外部端子之间的布线的约束，以及定时调整电路的数量是 根据将数据传输电路和IO块连接的总线（或共享总线）的布线长度确定为总线。

    Processor and program execution method capable of efficient program execution
    46.
    发明授权
    Processor and program execution method capable of efficient program execution 有权
    处理器和程序执行方法能够高效地执行程序

    公开(公告)号：US07921281B2

    公开(公告)日：2011-04-05

    申请号：US12110513

    申请日：2008-04-28

    申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

    发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

    IPC分类号： G06F9/48 ,  G06F9/52

    CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

    摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

    摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

    TWO-DIMENSIONAL FILTER ARITHMETIC DEVICE AND METHOD
    47.
    发明申请
    TWO-DIMENSIONAL FILTER ARITHMETIC DEVICE AND METHOD 有权
    二维滤波算术装置及方法

    公开(公告)号：US20100046851A1

    公开(公告)日：2010-02-25

    申请号：US12097994

    申请日：2006-11-21

    申请人： Akihiko Inoue ,  Tokuzo Kiyohara

    发明人： Akihiko Inoue ,  Tokuzo Kiyohara

    IPC分类号： G06K9/40 ,  H04N9/79

    CPC分类号： G06T3/4007 ,  G06T2200/28 ,  H04N19/82

    摘要： A two-dimensional filter arithmetic device comprises a picture memory (300), a line memory (400), a vertical filtering unit (100) which includes nine first filter modules installed in parallel, a buffer (500) for timing adjustments, and a horizontal filtering unit (200) which includes four second filter modules installed in parallel. From the line memory (400), the pixel values of nine full pels per line are inputted in parallel to the vertical filtering unit (100), nine vertically-filtered values of half pels are generated and inputted to the horizontal filtering unit (200); thereby, four two-dimensionally-filtered values of half pels are generated.

    摘要翻译： 二维滤波器运算装置包括图像存储器（300），行存储器（400），垂直滤波单元（100），其包括并联安装的九个第一滤波器模块，用于定时调整的缓冲器（500） 水平过滤单元（200），其包括并联安装的四个第二过滤器模块。 从行存储器（400），每行9个全像素的像素值与垂直滤波单元（100）并行地输入，产生九个垂直滤波的半像素值，并将其输入到水平滤波单元（200） ; 从而产生半个像素的四维二维滤波值。