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12 条记录 (耗时 0.013 秒)

    Processor
    2.
    发明授权
    Processor 有权
    处理器

    公开(公告)号：US07676527B2

    公开(公告)日：2010-03-09

    申请号：US10998012

    申请日：2004-11-29

    申请人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    发明人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    IPC分类号： G06F7/00

    CPC分类号： G06F7/76

    摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

    摘要翻译： 本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。 输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。 输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。 输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。 该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

    An EEPROM Circuit, a memory device having the EEPROM circuit and an IC card having the EEPROM circuit
    3.
    发明授权
    An EEPROM Circuit, a memory device having the EEPROM circuit and an IC card having the EEPROM circuit 失效
    EEPROM电路，具有EEPROM电路的存储器件和具有EEPROM电路的IC卡

    公开(公告)号：US5430675A

    公开(公告)日：1995-07-04

    申请号：US136308

    申请日：1993-10-13

    申请人： Shinji Yajima ,  Junji Michiyama ,  Nobuyuki Ikeda

    发明人： Shinji Yajima ,  Junji Michiyama ,  Nobuyuki Ikeda

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C13/00

    CPC分类号： G11C16/0433 ,  G11C16/10

    摘要： In an EEPROM, source electrodes S of memory cell transistors MT1 to MTn are grounded, via transistors MG1 to MGn. The source electrodes S are separated from each other so as to maintain the source electrode S of each of the memory cell transistors MT1 to MTn at an open state, even when a leak path is formed by the memory cell transistor MTi in the written state (low threshold voltage). In the EEPROM, an EPROM circuit in which the write operation can be continuously performed without the erase operation can be obtained. Further, an EEPROM circuit having the nonerasable region (the region which functions as the EPROM) and the erasable region (the region which functions as the EEPROM) can be also provided.

    摘要翻译： 在EEPROM中，存储单元晶体管MT1〜MTn的源极S通过晶体管MG1〜MGn接地。 源电极S彼此分离，以便即使当存储单元晶体管MTi在写入状态下形成泄漏路径时，也将存储单元晶体管MT1至MTn的源电极S保持在打开状态（ 低阈值电压）。 在EEPROM中，可以获得其中可以连续执行写入操作而不进行擦除操作的EPROM电路。 此外，还可以提供具有不可擦除区域（用作EPROM的区域）和可擦除区域（用作EEPROM的区域）的EEPROM电路。

    Arithmetic unit
    4.
    发明申请
    Arithmetic unit 有权

    公开(公告)号：US20050108307A1

    公开(公告)日：2005-05-19

    申请号：US10998012

    申请日：2004-11-29

    申请人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    发明人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    IPC分类号： G06F7/76 ,  G06F7/00 ,  H04B14/04

    CPC分类号： G06F7/76

    摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

    Nonvolatile semiconductor memory
    5.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US06191974B1

    公开(公告)日：2001-02-20

    申请号：US09321092

    申请日：1999-05-27

    申请人： Yoichi Nishida ,  Tomonori Kataoka ,  Ikuo Fuchigami ,  Tomoo Kimura ,  Junji Michiyama ,  Satoshi Koutaka

    发明人： Yoichi Nishida ,  Tomonori Kataoka ,  Ikuo Fuchigami ,  Tomoo Kimura ,  Junji Michiyama ,  Satoshi Koutaka

    IPC分类号： G11C1604

    CPC分类号： G11C16/32

    摘要： There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means 51 for generating timing signals which make a memory core unit 4 perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means 51 generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.

    摘要翻译： 提供了能够稳定运行并执行高速存取操作的非易失性半导体存储器。 用于产生使存储器核心单元4执行访问操作的定时信号的定时产生装置51使用相同周期和不同相位的第一和第二时钟。 定时产生装置51根据第一时钟产生多个读取访问事件中的至少一个前半个事件的定时信号，该第一时钟的相位在第二时钟的相位之前，并产生用于处理第二时钟的定时信号 剩下的事件，按照第二个时钟。

    Integrated circuit for video/audio processing
    6.
    发明授权
    Integrated circuit for video/audio processing 有权
    用于视频/音频处理的集成电路

    公开(公告)号：US08811470B2

    公开(公告)日：2014-08-19

    申请号：US10599494

    申请日：2005-04-01

    申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    IPC分类号： H04N7/12

    CPC分类号： G06F13/4027 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042

    摘要： An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

    摘要翻译： 用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。 集成电路包括微型计算机，其包括CPU，用于向外部设备输入/输出视频和音频流的流输入/输出，执行媒体处理的媒体处理器，该媒体处理包括至少一个压缩和解压缩视频，以及 输入到流输入/输出的音频流，将由媒体处理器进行媒体处理的视频和音频流转换成视频和音频信号并将这些信号输出到外部设备的AV输入/输出。 存储器接口控制微机，流输入/输出，媒体处理器和AV输入/输出之间的数据传输以及外部存储器。

    Arithmetic unit
    7.
    发明授权
    Arithmetic unit 有权
    算术单位

    公开(公告)号：US06901419B2

    公开(公告)日：2005-05-31

    申请号：US10366355

    申请日：2003-02-14

    申请人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    发明人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    IPC分类号： G06F7/76 ,  G06F7/00

    CPC分类号： G06F7/76

    摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

    摘要翻译： 本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。 输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。 输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。 输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。 该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

    Arithmetic device
    8.
    发明授权
    Arithmetic device 有权
    算术设备

    公开(公告)号：US06535899B1

    公开(公告)日：2003-03-18

    申请号：US09445059

    申请日：2000-02-16

    申请人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    发明人： Shunichi Kuromaru ,  Koji Okamoto ,  Junji Michiyama

    IPC分类号： G06F700

    CPC分类号： G06F7/76

    摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

    摘要翻译： 本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。 输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。 输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。 输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。 该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

    Integated Circuit For Video/Audio Processing
    10.
    发明申请
    Integated Circuit For Video/Audio Processing 有权
    用于视频/音频处理的整数电路

    公开(公告)号：US20070286275A1

    公开(公告)日：2007-12-13

    申请号：US10599494

    申请日：2005-04-01

    申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    IPC分类号： H04B1/66 ,  G06F13/12

    CPC分类号： G06F13/4027 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042

    摘要： The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream I/O block 4 for inputting/outputting video and audio streams to and from an external device, a media processing block 3 for executing the media processing including at least one of the compression and decompression of the video and audio streams, etc. inputted to the stream I/O block 4, an AV IO block 5 for converting the video and audio streams subjected to the media processing in the media processing block 3 into video and audio signals and outputting these signals to the external device, etc, and a memory IF block 6 for controlling the data transfer between the microcomputer block 2, the stream I/C block 4, the media processing block 3 and the AV IO block 5 and an external memory 9.

    摘要翻译： 本发明提供了一种用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。 该集成电路包括一个包括CPU的微处理器块2，用于向外部设备输入/输出视频和音频流的流I / O块4，用于执行媒体处理的媒体处理块3，包括至少一个 输入到流I / O块4的视频和音频流等的压缩和解压缩，用于将经过媒体处理块3中的媒体处理的视频和音频流转换成视频和音频信号的AV IO块5 并将这些信号输出到外部设备等;以及存储器IF块6，用于控制微计算机块2，流I / C块4，媒体处理块3和AV IO块5之间的数据传输，以及外部 记忆9。