公开(公告)号：US20160099348A1

公开(公告)日：2016-04-07

申请号：US14964017

申请日：2015-12-09

Applicant: Microchip Technology Incorporated

Inventor： Bomy Chen ,  Sonu Daryanani

IPC: H01L29/78 ,  G11C16/06 ,  H01L29/10 ,  G11C16/04 ,  H01L27/115 ,  H01L29/06

CPC classification number: H01L29/7816 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/2652 ,  H01L21/266 ,  H01L23/552 ,  H01L27/11524 ,  H01L27/11543 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7801 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

公开(公告)号：US09306055B2

公开(公告)日：2016-04-05

申请号：US14157337

申请日：2014-01-16

Applicant: Microchip Technology Incorporated

Inventor： Bomy Chen ,  Sonu Daryanani

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/552 ,  H01L29/08 ,  H01L29/10 ,  H01L27/115 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7816 ,  G11C16/0408 ,  G11C16/06 ,  H01L21/2652 ,  H01L21/266 ,  H01L23/552 ,  H01L27/11524 ,  H01L27/11543 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7801 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell.

Abstract translation: 形成集成的DMOS晶体管/ EEPROM单元的方法包括在衬底上形成第一掩模，使用第一掩模在衬底中形成漂移注入以对准漂移注入，同时在漂移注入上形成第一浮栅，以及 与所述漂移注入件间隔开的第二浮动栅极，形成覆盖所述第二浮动栅极并覆盖所述第一浮动栅极的一部分的第二掩模，使用所述第一浮动栅极的边缘在所述基板中形成基底注入以使所述基底 并且同时在第一浮动栅极上形成第一控制栅极，并且在第二浮栅上方形成第二控制栅极。 第一浮栅，第一控制栅，漂移注入和基极注入形成DMOS晶体管的组件，第二浮栅和第二控制栅形成EEPROM单元的组件。

公开(公告)号：US20140264248A1

公开(公告)日：2014-09-18

申请号：US14183831

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Sonu Daryanani

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1675

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract translation: 侧壁型存储单元（例如，CBRAM，ReRAM或PCM单元）可以包括底部电极，限定侧壁的顶部电极层和布置在底部和顶部电极层之间的电解质层，使得导电路径 经由电解质层限定在底部电极和顶部电极侧壁之间，其中底部电极层相对于水平衬底大致水平地延伸，并且顶部电极侧壁相对于水平衬底非水平地延伸，使得 当向单元施加正偏置电压时，导电路径在底电极和顶电极侧壁之间的非垂直方向（例如大致水平方向或其它非垂直方向）上生长。