公开(公告)号：US20220076729A1

公开(公告)日：2022-03-10

申请号：US17480685

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G11C11/4074 ,  G06F3/06

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：US20220068347A1

公开(公告)日：2022-03-03

申请号：US17470743

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US11133053B2

公开(公告)日：2021-09-28

申请号：US16863967

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/14 ,  G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US11133052B2

公开(公告)日：2021-09-28

申请号：US16740281

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G11C11/4074 ,  G06F3/06

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：US10957417B2

公开(公告)日：2021-03-23

申请号：US16786748

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C29/54 ,  G11C29/50 ,  G06F30/367 ,  G06F115/12 ,  G06F119/06

Abstract: Systems, apparatuses, and methods for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis or simulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals may be applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die.

公开(公告)号：US20210074335A1

公开(公告)日：2021-03-11

申请号：US17025628

申请日：2020-09-18

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F13/16

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US20200258593A1

公开(公告)日：2020-08-13

申请号：US16786748

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Beakkyu Choi

IPC: G11C29/54 ,  G11C29/50 ,  G06F30/367

Abstract: Systems, apparatuses, and methods for on-die memory power analytics and management are described. In some examples, the memory analytics and management may include a frequency-dependent analysis or simulation model of a memory die to determine an operating characteristic of the die. A set of ports of the memory die may be selected and one or more alternating current (AC) excitation signals may be applied to the ports to determine an impedance associated with the ports. The impedance may be used to determine one or more parameters (e.g., scattering, impedance) to analyze a die and for subsequently managing power distribution on the die. Analytics on a subset of ports on a die may be used to simulate the electrical response of the entire memory die and thus manage power delivery for the die.

公开(公告)号：US11721401B2

公开(公告)日：2023-08-08

申请号：US17877697

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C16/30 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C5/147

Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

公开(公告)号：US20230215488A1

公开(公告)日：2023-07-06

申请号：US18120136

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C5/14

CPC classification number: G11C11/4076 ,  G11C11/4074 ,  G11C5/147 ,  G11C5/143 ,  G11C5/14 ,  H03F3/45071

Abstract: Methods, systems, and devices for varying a time average for feedback of a memory system are described. An apparatus may include a voltage supply, a memory array, and a regulator coupled with the voltage supply and memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus may also include a voltage sensor configured to measure a second voltage of the memory array and a digital feedback circuit coupled with the memory array and regulator and configured to generate feedback comprising information averaged over a duration based at least in part on the second voltage measured by the voltage sensor and to transmit an analog signal to the regulator based at least in part on the feedback.

公开(公告)号：US20220351771A1

公开(公告)日：2022-11-03

申请号：US17243444

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh

IPC: G11C11/4076 ,  G11C11/4074

Abstract: Methods, systems, and devices for varying a time average for feedback of a memory system are described. An apparatus may include a voltage supply, a memory array, and a regulator coupled with the voltage supply and memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus may also include a voltage sensor configured to measure a second voltage of the memory array and a digital feedback circuit coupled with the memory array and regulator and configured to generate feedback comprising information averaged over a duration based at least in part on the second voltage measured by the voltage sensor and to transmit an analog signal to the regulator based at least in part on the feedback.