公开(公告)号：US20240231831A1

公开(公告)日：2024-07-11

申请号：US18612143

申请日：2024-03-21

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F15/80

CPC classification number: G06F9/3824 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/355 ,  G06F15/8053

Abstract: Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.

公开(公告)号：US11934836B2

公开(公告)日：2024-03-19

申请号：US17888410

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0891

CPC classification number: G06F9/3844 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/1032 ,  G06F2212/452

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

公开(公告)号：US11914756B2

公开(公告)日：2024-02-27

申请号：US17383123

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/71 ,  G06F9/30 ,  G06F21/60 ,  G06F12/14 ,  G06F12/0802

CPC classification number: G06F21/71 ,  G06F9/30178 ,  G06F12/0802 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402

Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a cache, a register, an execution unit, and an unscrambler. The processor can load the scrambled data into the cache; and the unscrambler may convert the scrambled data into unscrambled data just in time for the register or the execution unit during instruction execution. The unscrambled data can be an instruction, an address, or an operand of an instruction. Unscrambling can be performed just before loading the data item in a scrambled form from the cache into the register in an unscrambled form, or after the data item leaves the register in the scrambled form as input to the execution unit in the unscrambled form. The unscrambled data and the scrambled data may have the same set of bits arranged in different orders.

公开(公告)号：US11775308B2

公开(公告)日：2023-10-03

申请号：US17742340

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0842

CPC classification number: G06F9/3842 ,  G06F9/30098 ,  G06F12/0842 ,  G06F13/1684 ,  G06F2212/608

Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

公开(公告)号：US11720367B2

公开(公告)日：2023-08-08

申请号：US17707278

申请日：2022-03-29

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30058

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

公开(公告)号：US11561904B2

公开(公告)日：2023-01-24

申请号：US17170763

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/1009 ,  G06F12/14 ,  G06F9/455 ,  G06F21/53 ,  G11C11/408

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.

公开(公告)号：US20230004420A1

公开(公告)日：2023-01-05

申请号：US17942558

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/455

Abstract: Systems, apparatuses, and methods related to a virtual machine register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store, in the virtual machine register, an identifier of a virtual machine for which the processor is currently executing instructions in a current domain in the set of domains. For example, the processor can implement resource restriction/mapping and/or perform address translation for the virtual machine based on the identifier stored in the virtual machine register.

公开(公告)号：US20220276870A1

公开(公告)日：2022-09-01

申请号：US17742340

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0842

Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

公开(公告)号：US11422820B2

公开(公告)日：2022-08-23

申请号：US17189151

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0891

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

公开(公告)号：US11327862B2

公开(公告)日：2022-05-10

申请号：US16417526

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F11/26 ,  G06F9/30 ,  G06F11/22

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.