公开(公告)号：US20210081336A1

公开(公告)日：2021-03-18

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F13/10 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/12

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US10950318B2

公开(公告)日：2021-03-16

申请号：US16442430

申请日：2019-06-14

Applicant: Micron Technology, Inc.

Inventor： Jeffrey L. McVay ,  Samuel E. Bradshaw ,  Justin Eno

IPC: G11C16/34 ,  G11C29/52 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04

Abstract: Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.

公开(公告)号：US20210056405A1

公开(公告)日：2021-02-25

申请号：US16545837

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Sean Stephen Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz

IPC: G06N3/08 ,  G06F21/60

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.

公开(公告)号：US20200379919A1

公开(公告)日：2020-12-03

申请号：US16424420

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04L29/08

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US20190325956A1

公开(公告)日：2019-10-24

申请号：US16460538

申请日：2019-07-02

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw

IPC: G11C13/00

Abstract: A computer-implemented method for remediating disruptions to memory cells is described. The method includes writing user data to an aggressor memory cell and determining a write timestamp and an overwrite count associated with the aggressor memory cell. The write timestamp indicates a last write to the aggressor memory cell and the overwrite count indicates the number of writes to the aggressor memory cell during a time period. Based on the write timestamp and the overwrite count, an increment value is determined for use with a disturb counter associated with a neighbor memory cell of the aggressor memory cell. In particular, the determined increment value is used, in response to the write, to increment the disturb counter associated with the neighbor memory cell. When the disturb counter is greater than or equal to a disturb threshold, remediation for the neighbor memory cell is performed.

公开(公告)号：US20190294493A1

公开(公告)日：2019-09-26

申请号：US15926973

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw

IPC: G06F11/08 ,  G06F3/06 ,  G11C13/00

Abstract: A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.

公开(公告)号：US20190266047A1

公开(公告)日：2019-08-29

申请号：US16406775

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Samuel E. Bradshaw

IPC: G06F11/10

Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities. The controller can cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities.

公开(公告)号：US20190227869A1

公开(公告)日：2019-07-25

申请号：US15877008

申请日：2018-01-22

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw

IPC: G06F11/10 ,  G06F12/02

Abstract: A first tier of error correcting code operations on a data block may be performed. The first tier of error correcting code operations on the data block may be determined to be associated with an unsuccessful correction of an error of the data block. Responsive to determining that the first tier of error correcting code operations on the data block are associated with the unsuccessful correction of the error of the data block, a remix operation on the data block to change a logical to physical association of the data block from a first logical association to a second logical association may be performed.

公开(公告)号：US20180285187A1

公开(公告)日：2018-10-04

申请号：US15472957

申请日：2017-03-29

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Samuel E. Bradshaw

IPC: G06F11/07

CPC classification number: G06F11/0754 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/108

Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities. The controller can cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities.

公开(公告)号：US20250045096A1

公开(公告)日：2025-02-06

申请号：US18918998

申请日：2024-10-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/48 ,  G06F9/38 ,  G06F11/30 ,  G06F11/34 ,  G11C11/409

Abstract: Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.