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公开(公告)号：US11625170B2
公开(公告)日：2023-04-11
申请号：US17354658
申请日：2021-06-22
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G06F3/06
Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.
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公开(公告)号：US11561891B1
公开(公告)日：2023-01-24
申请号：US17500751
申请日：2021-10-13
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Todd Jackson Plum , Mark D. Ingram , Scott E. Schaefer , Scott D. Van De Graaff
Abstract: Methods, systems, and devices for adaptive user defined health indications are described. A host device may be configured to dynamically indicate adaptive health flags for monitoring health and wear information for a memory device. The host device may indicate, to a memory device, a first index. The first index may correspond to a first level of wear of a set of multiple indexed levels of wear for the memory device. The memory device may determine that a metric of the memory device satisfies the first level of wear and indicate, to the host device, that the first level of wear is satisfied. The host device may receive the indication that the first level of wear is satisfied and indicate, to the memory device, a second level of wear of the set of indexed levels of wear that is different than the first level of wear.
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公开(公告)号：US20220414034A1
公开(公告)日：2022-12-29
申请号：US17929643
申请日：2022-09-02
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Matthew A. Prather
IPC: G06F13/16 , G06F1/3206 , G06F1/3296 , G06F5/06 , G06F1/3234
Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
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公开(公告)号：US11436169B2
公开(公告)日：2022-09-06
申请号：US17207561
申请日：2021-03-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Matthew A. Prather
IPC: G11C5/14 , G06F13/16 , G06F5/06 , G06F1/3296 , G06F1/3234 , G06F1/3206
Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
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公开(公告)号：US20220238175A1
公开(公告)日：2022-07-28
申请号：US17580329
申请日：2022-01-20
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer
Abstract: Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.
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Patent Agency Ranking
公开(公告)号：US20220137880A1
公开(公告)日：2022-05-05
申请号：US17505046
申请日：2021-10-19
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Melissa I. Uribe
Abstract: Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.
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公开(公告)号：US11307929B2
公开(公告)日：2022-04-19
申请号：US16898354
申请日：2020-06-10
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
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公开(公告)号：US20220066867A1
公开(公告)日：2022-03-03
申请号：US17470584
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
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公开(公告)号：US11126498B2
公开(公告)日：2021-09-21
申请号：US16792820
申请日：2020-02-17
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
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公开(公告)号：US20210173562A1
公开(公告)日：2021-06-10
申请号：US17097766
申请日：2020-11-13
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G06F3/06
Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.
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