公开(公告)号：US20190121545A1

公开(公告)日：2019-04-25

申请号：US15791886

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F13/1642 ,  G06F3/0607 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/205

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US10152304B2

公开(公告)日：2018-12-11

申请号：US15995748

申请日：2018-06-01

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jesse F. Lovitt ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F7/58 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/408 ,  G11C7/06 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

公开(公告)号：US10032491B2

公开(公告)日：2018-07-24

申请号：US15399315

申请日：2017-01-05

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C11/4096

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

公开(公告)号：US09847110B2

公开(公告)日：2017-12-19

申请号：US14826481

申请日：2015-08-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C8/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C11/4096

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

公开(公告)号：US20170117020A1

公开(公告)日：2017-04-27

申请号：US15399315

申请日：2017-01-05

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C11/4096

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

公开(公告)号：US20240361933A1

公开(公告)日：2024-10-31

申请号：US18767519

申请日：2024-07-09

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Shashank Adavally ,  Jeffrey L. Scott ,  Robert M. Walker

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Apparatuses and methods related to port arbitration of a memory system are described. A memory system can receive a first number of transactions and a second transaction from a first traffic stream and a third number of transactions and a fourth transaction from a second traffic stream. The memory system can process the first number of transactions at least partially concurrently with the third number of transactions. Responsive to a total quantity of transactions of the first number of transactions and the second transaction being at least a threshold quantity of transactions, the second transaction can be processed by the memory system and, subsequent to processing the second transaction, the fourth transaction can be processed by the memory system.

公开(公告)号：US12112786B2

公开(公告)日：2024-10-08

申请号：US17464516

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jeffrey L. Scott ,  Laurent Isenegger ,  Robert M. Walker

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40603 ,  G06F13/1673

Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

公开(公告)号：US20240281141A1

公开(公告)日：2024-08-22

申请号：US18443956

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Better command scheduling in a memory controller can help improve memory device bandwidth utilization. A method for command scheduling in a memory controller can include processing commands of exclusively a first command type from a command queue including transmitting data in a first direction using a data bus for a first duration. Responsive to determining the first duration meets or exceeds a specified time or cycle limit, the bus can be turned around to accommodate transactions or commands of a second type. Following the bus turnaround, the method can include processing commands of exclusively a second command type from the command queue including transmitting data in a second direction using the data bus. The time or cycle limit can be statically or dynamically adjusted, for example, based on a read/write mix of commands in the command queue.

公开(公告)号：US12056375B2

公开(公告)日：2024-08-06

申请号：US17903743

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Shashank Adavally ,  Jeffrey L. Scott ,  Robert M. Walker

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Apparatuses and methods related to port arbitration of a memory system are described. A memory system can receive a first number of transactions and a second transaction from a first traffic stream and a third number of transactions and a fourth transaction from a second traffic stream. The memory system can process the first number of transactions at least partially concurrently with the third number of transactions. Responsive to a total quantity of transactions of the first number of transactions and the second transaction being at least a threshold quantity of transactions, the second transaction can be processed by the memory system and, subsequent to processing the second transaction, the fourth transaction can be processed by the memory system.

公开(公告)号：US20240078030A1

公开(公告)日：2024-03-07

申请号：US17903743

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Shashank Adavally ,  Jeffrey L. Scott ,  Robert M. Walker

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Apparatuses and methods related to port arbitration of a memory system are described. A memory system can receive a first number of transactions and a second transaction from a first traffic stream and a third number of transactions and a fourth transaction from a second traffic stream. The memory system can process the first number of transactions at least partially concurrently with the third number of transactions. Responsive to a total quantity of transactions of the first number of transactions and the second transaction being at least a threshold quantity of transactions, the second transaction can be processed by the memory system and, subsequent to processing the second transaction, the fourth transaction can be processed by the memory system.