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公开(公告)号：US20120012973A1
公开(公告)日：2012-01-19
申请号：US12836785
申请日：2010-07-15
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches.
摘要翻译： 公开了具有超低电容的横向瞬态电压抑制器。 抑制器包括第一类型衬底和布置在第一类型衬底中的至少一个二极管级联结构。 级联结构还包括至少一个第二类型轻掺杂阱和至少一个第一类型轻掺杂阱，其中在第二类型轻掺杂阱和第一类型轻掺杂阱中布置有两个重掺杂区。 级联结构邻近第二类型井，其中在第二类井中布置有三个重掺杂区域。 抑制器还包括布置在第一类型衬底中并且具有大于第二类型轻掺杂阱，第二类型阱和第一类型轻掺杂阱的深度的深度的多个深隔离沟槽。 每个掺杂的阱由沟槽隔离。
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公开(公告)号：US08431999B2
公开(公告)日：2013-04-30
申请号：US13072138
申请日：2011-03-25
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L27/0255 , H01L29/861
摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.
摘要翻译： 公开了一种低电容瞬态电压抑制器。 抑制器包括N型重掺杂衬底和形成在衬底上的外延层。 形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱 在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。 在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。 此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的 好。
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公开(公告)号：US20130003242A1
公开(公告)日：2013-01-03
申请号：US13612253
申请日：2012-09-12
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H05K1/0259
摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage.One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.
摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。
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公开(公告)号：US08237193B2
公开(公告)日：2012-08-07
申请号：US12837128
申请日：2010-07-15
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor for low-voltage applications. The suppressor includes an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further includes a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite conductivity types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.
摘要翻译： 用于低电压应用的横向瞬态电压抑制器。 抑制器包括N型重掺杂衬底和水平地布置在N型重掺杂衬底中的至少两个钳位二极管结构。 每个钳位二极管结构还包括在N型重掺杂衬底中布置的具有第一重掺杂区域和第二重掺杂区域的钳位阱。 第一和第二重掺杂区域分别属于相反的导电类型。 在N型重掺杂衬底中布置有多个深的隔离沟槽，其深度大于夹具阱的深度。 深的隔离沟槽可以很好地分离每个夹具。 本发明避免了巨大的漏电流适合于低电压应用。
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公开(公告)号：US08217462B2
公开(公告)日：2012-07-10
申请号：US12888151
申请日：2010-09-22
IPC分类号： H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L27/0259 , H01L29/866
摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.
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公开(公告)号：US08552530B2
公开(公告)日：2013-10-08
申请号：US12848531
申请日：2010-08-02
IPC分类号： H01L29/06
CPC分类号： H01L27/0259
摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
摘要翻译： 公开了一种用于保护电子设备的垂直瞬态电压抑制器。 垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域 型重掺杂区域耦合到第一类型重掺杂区域。
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公开(公告)号：US08304838B1
公开(公告)日：2012-11-06
申请号：US13216016
申请日：2011-08-23
IPC分类号： H01L21/00
CPC分类号： H01L27/0255
摘要： An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.
摘要翻译： 公开了一种静电放电保护器件结构，其包括半导体衬底和布置在半导体衬底上的N型外延层。 在N型外延层中布置有至少一个快速反应级联结构，其中快速回退级联结构还包括布置在N型外延层中的第一和第二P型阱。 排列在第一P型井中的第一和第二重掺杂区域分别属于相反的类型。 并且，排列在第二P型阱中的第三和第四重掺杂区域分别属于相反的类型，其中第二和第三重掺杂区域分别属于相反的类型并且彼此电连接。 当第一重掺杂区域接收到ESD信号时，ESD电流通过第一P型阱，N型外延层和第二P型阱从第一重掺杂区流动到第四重掺杂区。
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公开(公告)号：US07598797B2
公开(公告)日：2009-10-06
申请号：US12018659
申请日：2008-01-23
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/071
摘要： A charge pump circuit with bipolar output comprises a first set of switch device capable of selectively connecting two terminals of a first transfer capacitor to a voltage source and a ground terminal, respectively, a second set of switch device capable of selectively connecting the two terminals of the first transfer capacitor to a grounded first storage capacitor and the voltage source, respectively, a third set of switch device capable of selectively connecting two terminals of a second transfer capacitor to the first transfer capacitor connected to the voltage source and the ground terminal, respectively, and a fourth set of switch device capable of selectively connecting the two terminals of the second transfer capacitor to a grounded second storage capacitor and the ground terminal, respectively. These four sets of switch devices totally have nine switches, and are collocated with clock signals to be selectively driven by a four-phase signal or a two-phase signal so as to produce bipolar voltages with magnitudes higher than the input voltage and also accomplish the highest conversion efficiency.
摘要翻译： 具有双极性输出的电荷泵电路包括第一组开关装置，其能够分别选择性地将第一转移电容器的两个端子连接到电压源和接地端子，第二组开关装置能够选择性地将两个端子 第一传输电容器分别连接到接地的第一存储电容器和电压源，第三组开关器件能够分别选择性地将第二传输电容器的两个端子连接到连接到电压源和接地端子的第一传输电容器 以及第四组开关装置，其能够分别选择性地将第二转移电容器的两个端子连接到接地的第二存储电容器和接地端子。 这四组开关装置总共有九个开关，并配有时钟信号，由四相信号或两相信号选择性驱动，以产生高于输入电压的双极性电压，并且还完成了 转换效率最高。
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公开(公告)号：US20090097174A1
公开(公告)日：2009-04-16
申请号：US11907206
申请日：2007-10-10
IPC分类号： H02H9/04
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
摘要翻译： 提供一种适用于具有分离电源域的集成电路中的ESD保护电路。 电路包括耦合在第一电源域中的第一电路和第二电源域中的第二电路之间的P型MOSFET。 P型MOSFET的源极端子连接到用于连接第一电路和第二电路的连接节点。 P型MOSFET的栅极端子耦合到第二电源域的正电源线。 P型MOSFET的漏极端子耦合到第二电源域的负电源线。 P型MOSFET的体式端子也耦合到连接节点。
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