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54 条记录 (耗时 0.032 秒)

    LEVEL SHIFT CIRCUIT, SIGNAL DRIVE CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE
    41.
    发明申请
    LEVEL SHIFT CIRCUIT, SIGNAL DRIVE CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE 有权
    水平移位电路，信号驱动电路，显示设备和电子设备

    公开(公告)号：US20110157145A1

    公开(公告)日：2011-06-30

    申请号：US12968953

    申请日：2010-12-15

    申请人： Yoshihiko Toyoshima ,  Seiichiro Jinta

    发明人： Yoshihiko Toyoshima ,  Seiichiro Jinta

    IPC分类号： H03L5/00 ,  G06F3/038

    CPC分类号： H03K19/018557 ,  G09G3/3266 ,  G09G3/3611 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286

    摘要： A level shift circuit includes: a first and a second output transistor outputting voltages derived from a first and a second power source voltage, respectively; a first and a second input transistor outputting, based on a first input pulse signal, a first voltage for turning ON the first output transistor and a second voltage for turning OFF the second output transistor, respectively; a third and a fourth input transistor outputting, based on a second input pulse signal, a third voltage for turning OFF the first output transistor and a fourth voltage for turning ON the second output transistor, respectively; a first bootstrap circuit enlarging an amplitude of the first voltage and supplying the same to the first output transistor; and a first voltage compensation circuit, based on a third input pulse signal, making, at an end timing of the first input pulse signal, a voltage change in a direction opposite to that of a voltage fluctuation caused in the first voltage due to a parasitic capacitance in the first input transistor.

    摘要翻译： 电平移位电路包括：分别从第一和第二电源电压输出电压的第一和第二输出晶体管; 第一和第二输入晶体管，分别基于第一输入脉冲信号输出用于接通第一输出晶体管的第一电压和用于关断第二输出晶体管的第二电压; 第三输入晶体管和第四输入晶体管，分别基于第二输入脉冲信号输出用于使所述第一输出晶体管截止的第三电压和用于接通所述第二输出晶体管的第四电压; 第一自举电路，放大第一电压的幅度并将其提供给第一输出晶体管; 以及基于第三输入脉冲信号的第一电压补偿电路，在所述第一输入脉冲信号的结束定时，使与所述第一电压中由于寄生物引起的电压波动相反的方向的电压变化 第一输入晶体管中的电容。

    Level shift circuit and shift register and display device
    44.
    发明申请
    Level shift circuit and shift register and display device 有权
    电平移位电路和移位寄存器及显示装置

    公开(公告)号：US20060197554A1

    公开(公告)日：2006-09-07

    申请号：US11365949

    申请日：2006-03-02

    申请人： Seiichiro Jinta

    发明人： Seiichiro Jinta

    IPC分类号： H03K19/0175

    CPC分类号： G11C19/184 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03K19/01855

    摘要： A level shift circuit, a shift register, and a display device in which circuit operation is resistant to influence of variations in characteristics of elements such as transistors. The level shift circuit, includes a first switch turning on or off in accordance with a voltage of a first node, switching ON and OFF when the voltage is a first threshold value, and outputting a first voltage when ON state; a second switch turning on or off in accordance with the voltage of a second node, switching ON and OFF when the voltage is a second threshold value, and outputting a second voltage when ON state; a first capacitor receiving a first input signal at one terminal and connected at the other terminal to the first node; a second capacitor receiving a second input signal at one terminal, and connected at the other terminal to the second node; and a circuit for setting the voltage of the first node at the first threshold value and setting the voltage of the second node at the second threshold value in a predetermined period and setting the first node and the second node in a floating state after the predetermined period.

    摘要翻译： 电平移位电路，移位寄存器和显示装置，其中电路操作抵抗诸如晶体管的元件的特性变化的影响。 电平移位电路包括根据第一节点的电压接通或关断的第一开关，当电压为第一阈值时接通和断开，并且在接通状态时输出第一电压; 第二开关根据第二节点的电压接通或断开，当电压为第二阈值时接通和断开，并且在接通状态时输出第二电压; 第一电容器，其在一个端子处接收第一输入信号，并且在另一端子处连接到所述第一节点; 在一个终端接收第二输入信号并在另一个终端处连接到第二节点的第二电容器; 以及电路，用于将所述第一节点的电压设置在所述第一阈值，并且将所述第二节点的电压设定在所述第二阈值的预定周期，并且在所述预定时段之后将所述第一节点和所述第二节点设置为浮动状态 。

    Scanning drive circuit and display device including the same
    46.
    发明授权
    Scanning drive circuit and display device including the same 有权
    扫描驱动电路和包括其的显示装置

    公开(公告)号：US08411016B2

    公开(公告)日：2013-04-02

    申请号：US12453754

    申请日：2009-05-21

    申请人： Takao Tanikame ,  Seiichiro Jinta

    发明人： Takao Tanikame ,  Seiichiro Jinta

    IPC分类号： G06G3/36

    CPC分类号： G09G3/3266 ,  G09G3/32 ,  G09G3/3208 ,  G09G3/325 ,  G09G5/001 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2310/0286

    摘要： A scan driving circuit and a display device, the display device including display elements two-dimensionally disposed in a matrix; scanning lines, initialization control lines, and display control lines extending in a first direction; and data lines extending in a second direction different from the first direction. The scan driving circuit includes a shift register portion and a logic circuit portion, and generates scan signals and initialization signals, both based on two or more enable signals, and control signals. The scan driving circuit is configured such that changing the width of a start pulse (and thereby the ratio of a light emitting period to a non-light emitting period) does not affect the scan signals or the initialization signals.

    摘要翻译： 一种扫描驱动电路和显示装置，所述显示装置包括以二维方式设置在矩阵中的显示元件; 扫描线，初始化控制线和沿第一方向延伸的显示控制线; 以及沿与第一方向不同的第二方向延伸的数据线。 扫描驱动电路包括移位寄存器部分和逻辑电路部分，并且基于两个或多个使能信号和控制信号产生扫描信号和初始化信号。 扫描驱动电路被配置为使得开始脉冲的宽度（从而使发光周期与非发光周期的比率）的改变不影响扫描信号或初始化信号。

    Display device and electronic apparatus
    47.
    发明授权
    Display device and electronic apparatus 有权
    显示设备和电子设备

    公开(公告)号：US08159424B2

    公开(公告)日：2012-04-17

    申请号：US12458810

    申请日：2009-07-23

    申请人： Tetsuro Yamamoto ,  Junichi Yamashita ,  Katsuhide Uchino ,  Seiichiro Jinta

    发明人： Tetsuro Yamamoto ,  Junichi Yamashita ,  Katsuhide Uchino ,  Seiichiro Jinta

    IPC分类号： G09G3/30

    CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2320/043

    摘要： Disclosed herein is a sampling transistor in an embodiment of the present invention is kept at the on-state with a time width shorter than one horizontal cycle, during the period from the rising of a control pulse supplied from a scanner to a scan line WS to the falling of the control pulse, and samples a video signal from a signal line SL to write the video signal to a hold capacitor. The sampling transistor includes the channel region between the source and the drain and has a sandwich gate structure in which a shield that electrically shields the channel region is disposed on the other side of the channel region. This suppresses change in the threshold voltage of the sampling transistor.

    摘要翻译： 这里公开的是，在从扫描仪提供到扫描线WS的控制脉冲的上升期间，本发明的实施例中的采样晶体管保持处于导通状态，时间宽度短于一个水平周期， 控制脉冲的下降，并对来自信号线SL的视频信号进行采样，以将视频信号写入保持电容器。 采样晶体管包括源极和漏极之间的沟道区域，并且具有夹层栅极结构，其中电屏蔽通道区域的屏蔽设置在沟道区域的另一侧。 这抑制了采样晶体管的阈值电压的变化。

    Semiconductor device, display panel, and electronic apparatus
    48.
    发明授权
    Semiconductor device, display panel, and electronic apparatus 失效

    公开(公告)号：US07800576B2

    公开(公告)日：2010-09-21

    申请号：US12457570

    申请日：2009-06-16

    申请人： Seiichiro Jinta

    发明人： Seiichiro Jinta

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/0866 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2320/043 ,  G11C19/184 ,  G11C19/28

    摘要： A single-channel thin-film transistor buffer includes a first output stage including first and second thin-film transistors connected in series, a seventh thin-film transistor having one main electrode connected to a control electrode of the first thin-film transistor (first control line), the other main electrode connected to a power source of the second thin-film transistor, and a control electrode connected to a second control line, an eighth thin-film transistor having one main electrode connected to a control electrode of the second thin-film transistor (second control line), the other main electrode connected to the power source of the second thin-film transistor, and a control electrode connected to the first control line, and an eleventh thin-film transistor having a control electrode connected to an output terminal of a second output stage connected in parallel with the first output stage and one main electrode connected to the first control line.

    Display device and electronic apparatus
    49.
    发明申请
    Display device and electronic apparatus 有权
    显示设备和电子设备

    公开(公告)号：US20100026612A1

    公开(公告)日：2010-02-04

    申请号：US12458810

    申请日：2009-07-23

    申请人： Tetsuro Yamamoto ,  Junichi Yamashita ,  Katsuhide Uchino ,  Seiichiro Jinta

    发明人： Tetsuro Yamamoto ,  Junichi Yamashita ,  Katsuhide Uchino ,  Seiichiro Jinta

    IPC分类号： G09G3/30

    CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2320/043

    摘要： Disclosed herein is a sampling transistor in an embodiment of the present invention is kept at the on-state with a time width shorter than one horizontal cycle, during the period from the rising of a control pulse supplied from a scanner to a scan line WS to the falling of the control pulse, and samples a video signal from a signal line SL to write the video signal to a hold capacitor. The sampling transistor includes the channel region between the source and the drain and has a sandwich gate structure in which a shield that electrically shields the channel region is disposed on the other side of the channel region. This suppresses change in the threshold voltage of the sampling transistor.

    摘要翻译： 这里公开的是，在从扫描仪提供到扫描线WS的控制脉冲的上升期间，本发明的实施例中的采样晶体管保持处于导通状态，时间宽度短于一个水平周期， 控制脉冲的下降，并对来自信号线SL的视频信号进行采样，以将视频信号写入保持电容器。 采样晶体管包括源极和漏极之间的沟道区域，并且具有夹层栅极结构，其中电屏蔽通道区域的屏蔽设置在沟道区域的另一侧。 这抑制了采样晶体管的阈值电压的变化。