公开(公告)号：US20230298861A1

公开(公告)日：2023-09-21

申请号：US18052589

申请日：2022-11-04

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Tomoki NAGAE ,  Yusuke OGISO ,  Takuya YOTO

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/3244 ,  H01J37/32724 ,  H01L21/6833

Abstract: A member for semiconductor manufacturing apparatus includes: a ceramic plate having a wafer placement surface on its upper surface; and a porous plug that is disposed in a plug insertion hole penetrating the ceramic plate in a up-down direction, and allows a gas to flow, wherein the porous plug has a first porous member exposed to the wafer placement surface, and a second porous member having an upper surface covered by the first porous member, the first porous member is higher in purity and smaller in thickness than the second porous member, and the second porous member is higher in porosity than the first porous member.

公开(公告)号：US20230197500A1

公开(公告)日：2023-06-22

申请号：US18168032

申请日：2023-02-13

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Hiroshi TAKEBAYASHI ,  Tatsuya KUNO

IPC: H01L21/687 ,  H01L23/373

CPC classification number: H01L21/68721 ,  H01L23/3731 ,  H01L23/3736

Abstract: A wafer placement table includes a ceramic substrate having a wafer placement surface on an upper surface thereof and containing an electrode therein, a cooling substrate made of a metal-ceramic composite and having a cooling medium passage therein, and a metal joining layer configured to join a lower surface of the ceramic substrate to an upper surface of the cooling substrate. A thickness of a lower part of the cooling substrate below the cooling medium passage is greater than or equal to 13 mm, or greater than or equal to 43% of an overall thickness of the cooling substrate.

公开(公告)号：US20230146001A1

公开(公告)日：2023-05-11

申请号：US17819670

申请日：2022-08-15

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01L21/67 ,  H01J37/32

CPC classification number: H01L21/67109 ,  H01J37/32642 ,  H01L21/6833

Abstract: A wafer placement table includes a central ceramic base that has an upper surface including a wafer placement surface, an outer circumferential ceramic base that has an upper surface including a focus ring placement surface, and a cooling base that includes a central portion, an outer circumferential portion, and a coupler that couples the central portion and the outer circumferential portion with each other. The cooling base has a central refrigerant flow path that is formed in the central portion and an outer circumferential refrigerant flow path that is formed in the outer circumferential portion. The coupler has an upward groove that open from an upper surface and that have an annular shape, and a downward groove that opens from a lower surface, that have a ceiling surface higher than a bottom surface of the upward groove, and that have an annular shape.

公开(公告)号：US20230057107A1

公开(公告)日：2023-02-23

申请号：US17805237

申请日：2022-06-03

Applicant: NGK Insulators, Ltd.

Inventor： Hiroshi TAKEBAYASHI ,  Tatsuya KUNO ,  Seiya INOUE

IPC: H01J37/32 ,  C23C16/458

Abstract: A wafer placement table includes a ceramic base, a cooling base, and a bonding layer. The ceramic base includes an outer peripheral part having an annular focus ring placement surface on an outer peripheral side of a central part having a circular wafer placement surface. The cooling base contains metal. The bonding layer bonds the ceramic base with the cooling base. The outer peripheral part of the ceramic base has a thickness of less than or equal to 1 mm and does not incorporate an electrode.