公开(公告)号：US20240038567A1

公开(公告)日：2024-02-01

申请号：US18170129

申请日：2023-02-16

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Natsuki HIRATA ,  Kenji YONEMOTO

IPC: H01L21/683

CPC classification number: H01L21/6833 ,  H01J37/32724

Abstract: A member for a semiconductor manufacturing apparatus, includes: a ceramic plate that has a ceramic plate through hole; an electroconductive base plate that has a base plate through hole and that is disposed on a lower surface side of the ceramic plate; an insulating sleeve which is inserted into the base plate through hole and of which an outer peripheral surface is adhered to an inner peripheral surface of the base plate through hole via an adhesion layer; and a sleeve through hole that passes through the insulating sleeve in the up-down direction and that communicates with the ceramic plate through hole. The insulating sleeve has a tool engaging portion that is engageable with an external tool, and upon being engaged with the external tool, the tool engaging portion transmits rotation torque of the external tool to the insulating sleeve.

公开(公告)号：US20230343565A1

公开(公告)日：2023-10-26

申请号：US18171837

申请日：2023-02-21

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32724 ,  H01L21/6833 ,  H01J2237/2007 ,  H01J2237/002

Abstract: A wafer placement table includes: a ceramic substrate having a wafer placement surface at an upper surface, and incorporating an electrode; a cooling substrate which is bonded to a lower surface of the ceramic substrate, and in which a refrigerant flow path is formed; a power supply terminal connected to the electrode; and a power supply terminal hole vertically penetrating the cooling substrate and storing the power supply terminal. The power supply terminal hole intersects with the refrigerant flow path.

公开(公告)号：US20230343564A1

公开(公告)日：2023-10-26

申请号：US18170025

申请日：2023-02-16

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO

IPC: H01J37/32

CPC classification number: H01J37/32724 ,  H01J37/32807

Abstract: A wafer placement table includes a ceramic substrate having a wafer placement surface on an upper surface thereof and containing an electrode therein; a conductive substrate disposed adjacent to a lower surface of the ceramic substrate, serving also as a plasma generating electrode, and having the same diameter as the ceramic substrate; a support substrate disposed adjacent to a lower surface of the conductive substrate, having a greater diameter than the conductive substrate, and electrically insulated from the conductive substrate; and a mounting flange constituting a part of the support substrate and radially extending out of the conductive substrate.

公开(公告)号：US20230238224A1

公开(公告)日：2023-07-27

申请号：US18056802

申请日：2022-11-18

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Shinya YOSHIDA ,  Tomoki NAGAE ,  Yusuke OGISO ,  Takuya YOTO

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32715 ,  H01J37/3244 ,  H01L21/6833 ,  H01J2237/327

Abstract: A member for semiconductor manufacturing apparatus has a ceramic plate, a porous plug, an insulating lid, and pores. The ceramic plate has a wafer placement surface as an upper surface. The porous plug is disposed in a plug insertion hole penetrating the ceramic plate in an up-down direction, and allows a gas to flow. The insulating lid is provided in contact with an upper surface of the porous plug, and exposed to the wafer placement surface. A plurality of pores are provided in the insulating lid, and penetrate the insulating lid in an up-down direction.

公开(公告)号：US20230146815A1

公开(公告)日：2023-05-11

申请号：US17819663

申请日：2022-08-15

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Ikuhisa MORIOKA

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/68714 ,  H01L21/67109

Abstract: A wafer placement table includes a ceramic base having a wafer placement surface on its top surface where a wafer is able to be placed and incorporating an electrode; a cooling base having a refrigerant flow channel; and a bonding layer that bonds the ceramic base with the cooling base, wherein in an area that overlaps the wafer placement surface in plan view of the refrigerant flow channel, a cross-sectional area of the refrigerant flow channel at a most downstream part of the refrigerant flow channel is less than the cross-sectional area at a most upstream part of the refrigerant flow channel.

公开(公告)号：US20230115033A1

公开(公告)日：2023-04-13

申请号：US17809567

申请日：2022-06-29

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01L21/683

Abstract: A member for semiconductor manufacturing apparatus includes a ceramic plate that has an upper surface including a wafer placement surface and that contains an electrode; a plug insertion hole that is formed as at least a portion of a through-hole extending through the ceramic plate in an up-down direction, an internal thread portion being on an inner circumferential surface around the plug insertion hole; and an insulating plug that includes an external thread portion screwed on the internal thread portion on an outer circumferential surface and that allows gas to pass therethrough.

公开(公告)号：US20230111137A1

公开(公告)日：2023-04-13

申请号：US17807401

申请日：2022-06-17

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE ,  Hiroshi TAKEBAYASHI

IPC: H01J37/32 ,  H01L21/683 ,  C23C16/458

Abstract: A wafer placement table includes a ceramic base having a wafer placement surface on its top surface and incorporating an electrode, a cooling base in which a refrigerant flow channel is formed, and a metal bonding layer that bonds the ceramic base with the cooling base. The cooling base includes a ceiling base made of a metal matrix composite material or a low thermal expansion metal material and defining a ceiling of the refrigerant flow channel, a grooved base of which a main component is made of the same ceramic material as a main component of the ceramic base and on a top surface of which a flow channel groove defining a bottom and a side wall of the refrigerant flow channel is provided, and a metal ceiling bonding layer that bonds a bottom surface of the ceiling base with the top surface of the grooved base.

公开(公告)号：US20240297062A1

公开(公告)日：2024-09-05

申请号：US18582759

申请日：2024-02-21

Applicant: NGK INSULATORS, LTD.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Masaki ISHIKAWA ,  Taro USAMI ,  Ren NAKAMURA ,  Natsuki HIRATA ,  Kenji YONEMOTO

IPC: H01L21/683

CPC classification number: H01L21/6833

Abstract: A wafer placement table includes a ceramic plate having a wafer placement surface on its top surface and incorporating an electrode; an electrically conductive plate joined to a bottom surface of the ceramic plate; a ceramic plate penetrating part extending through the ceramic plate; an electrically insulating gas passage plug provided in the ceramic plate penetrating part and that allows gas to pass inside; a gas introduction passage provided at least inside the electrically conductive plate and communicating with the ceramic plate penetrating part; and an electrically conductive gas passage part provided in the gas introduction passage, being in contact with a bottom surface of the electrically insulating gas passage plug, being electrically continuous with the electrically conductive plate, and that allows gas to pass inside.

公开(公告)号：US20240234199A9

公开(公告)日：2024-07-11

申请号：US18299130

申请日：2023-04-12

Applicant: NGK INSULATORS, LTD.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01L21/687 ,  H01J37/32

CPC classification number: H01L21/68785 ,  H01J37/3244 ,  H01J37/32724 ,  H01L21/68757 ,  H01J2237/002

Abstract: A wafer placement table includes: a ceramic plate including a wafer placement portion having a reference surface on which a number of small protrusions are provided; a cooling plate including a refrigerant flow path; a joining layer with which the ceramic plate and the cooling plate are joined; a recessed groove provided in the reference surface and having a bottom surface positioned lower than the reference surface; a plug arrangement hole passing through the ceramic plate and being open to the bottom surface of the recessed groove; a porous plug disposed in the plug arrangement hole, the porous plug having a top surface positioned at the same height as the bottom surface of the recessed groove and allowing gas to flow; and a gas supply path through which gas is supplied to the porous plug.

公开(公告)号：US20230343566A1

公开(公告)日：2023-10-26

申请号：US18173889

申请日：2023-02-24

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32724 ,  H01L21/6833 ,  H01J2237/2007 ,  H01J2237/002

Abstract: A wafer placement includes an alumina substrate having a wafer placement surface at an upper surface, and incorporating an electrode; a brittle cooling substrate which is bonded to a lower surface of the alumina substrate, and in which a refrigerant flow path is formed; and a ductile connection member stored in a storage hole opened in a lower surface of the cooling substrate in a state of restricted axial rotation and in a state of being engaged with an engagement section of the storage hole, the ductile connection member having a male thread section or a female thread section, wherein the storage hole is provided in the refrigerant flow path.