公开(公告)号：US08726114B1

公开(公告)日：2014-05-13

申请号：US13672799

申请日：2012-11-09

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar ,  Gaurav Agarwal

IPC: G01R31/28

CPC classification number: G11C29/36 ,  G11C11/41 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/5602

Abstract: Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.

Abstract translation: 描述了与静态随机存取存储器（SRAM）的高速测试相关联的系统，方法和其它实施例。 在一个实施例中，一种方法包括将存储器设备的多级流水线加载到用于测试静态随机存取存储器（SRAM）的控制模式。 通过产生至少部分地基于来自触发器的多级流水线的控制模式的测试输入来测试SRAM。 测试输入通过处于SRAM的核心时钟速度的一系列时钟周期提供给SRAM。