公开(公告)号：US08726114B1

公开(公告)日：2014-05-13

申请号：US13672799

申请日：2012-11-09

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar ,  Gaurav Agarwal

IPC: G01R31/28

CPC classification number: G11C29/36 ,  G11C11/41 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/5602

Abstract: Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.

Abstract translation: 描述了与静态随机存取存储器（SRAM）的高速测试相关联的系统，方法和其它实施例。 在一个实施例中，一种方法包括将存储器设备的多级流水线加载到用于测试静态随机存取存储器（SRAM）的控制模式。 通过产生至少部分地基于来自触发器的多级流水线的控制模式的测试输入来测试SRAM。 测试输入通过处于SRAM的核心时钟速度的一系列时钟周期提供给SRAM。

公开(公告)号：US10073139B2

公开(公告)日：2018-09-11

申请号：US14502509

申请日：2014-09-30

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar

IPC: G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/31705

Abstract: Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.

公开(公告)号：US20160091565A1

公开(公告)日：2016-03-31

申请号：US14502509

申请日：2014-09-30

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar

IPC: G01R31/3177

CPC classification number: G01R31/31726 ,  G01R31/31705

Abstract: Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.

Abstract translation: 本公开的实现涉及用于利用一个或多个异步时钟域执行微处理器或其他计算设计的循环确定性功能测试的装置和/或方法。 通常，该方法/装置涉及利用微处理器设计中的观察总线将数据从芯片设计中转移到输出总线。 此外，为了确保芯片的输出与测试仪时钟同步，观察总线可将信息从观察总线馈送到一个或多个先进先出（FIFO）数据缓冲器。 在测试期间，可以以与测试器时钟同步的速率将存储在数据缓冲器中的数据提供给芯片的输出引脚，使得输出作为循环确定性出现在测试装置上。 此外，在观察总线或电路设计中可以采用一个或多个机制来控制数据到数据缓冲器中的输入速率。