公开(公告)号：US08972767B2

公开(公告)日：2015-03-03

申请号：US13679690

申请日：2012-11-16

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F1/12 ,  G06F1/04 ,  G06F1/00

CPC classification number: G06F1/12

Abstract: Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat.

Abstract translation: 本公开的实现涉及用于将至少一个新激活的处理器与至少一个以前运行的处理器同步的装置和/或方法。 每个处理器配置为产生心跳并根据STICK进行操作。 当添加先前停用的处理器时，每个活动处理器的心跳被复位，并且当前的STICK在下一个心跳上传输到新激活的处理器。 然后，新激活的处理器可以将心跳周期添加到所获取的STICK，并且在下一个心跳之后开始递增STICK和正常操作。

公开(公告)号：US08726114B1

公开(公告)日：2014-05-13

申请号：US13672799

申请日：2012-11-09

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar ,  Gaurav Agarwal

IPC: G01R31/28

CPC classification number: G11C29/36 ,  G11C11/41 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/5602

Abstract: Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.

Abstract translation: 描述了与静态随机存取存储器（SRAM）的高速测试相关联的系统，方法和其它实施例。 在一个实施例中，一种方法包括将存储器设备的多级流水线加载到用于测试静态随机存取存储器（SRAM）的控制模式。 通过产生至少部分地基于来自触发器的多级流水线的控制模式的测试输入来测试SRAM。 测试输入通过处于SRAM的核心时钟速度的一系列时钟周期提供给SRAM。