公开(公告)号：US20230088825A1

公开(公告)日：2023-03-23

申请号：US17994591

申请日：2022-11-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/196 ,  H04N19/105 ,  H04N19/14 ,  H04N19/176 ,  H04N19/436

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives a correction parameter using only a neighboring reconstructed image that neighbors a processing unit which has a determined size and is located at an upper left of a current block to be processed in an image, among neighboring reconstructed images that neighbor the current block, and performs correction processing of the current block based on the correction parameter derived, when the current block has a size larger than the determined size.

公开(公告)号：US20230059074A1

公开(公告)日：2023-02-23

申请号：US17977184

申请日：2022-10-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE

IPC: H04N19/70 ,  H04N19/31

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, in the case where a video parameter set is used for encoding a video, the circuitry writes a first parameter into the video parameter set. The first parameter indicates the maximum number of one or more temporal sublayers in a layer set unit. The circuitry writes a second parameter into a sequence parameter set. The second parameter indicates the maximum number of one or more temporal sublayers in a sequence unit. In the case where the video parameter set is used for encoding the video, the second parameter is limited to less than or equal to the first parameter. In the case where the video parameter set is not used for encoding the video, the second parameter is limited to less than or equal to a fixed value.

公开(公告)号：US20230042791A1

公开(公告)日：2023-02-09

申请号：US17945629

申请日：2022-09-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Sughosh Pavan SHASHIDHAR ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/46 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.

公开(公告)号：US20230015486A1

公开(公告)日：2023-01-19

申请号：US17941219

申请日：2022-09-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/172 ,  H04N19/182 ,  H04N19/70 ,  H04N19/85

Abstract: An encoder includes circuitry and memory coupled to circuitry. In operation, circuitry: designs each of subpictures included in a picture in such a manner that at least one pixel included in the subpicture is included in a conformance cropping window; encodes arrangement information indicating an arrangement of each of the subpictures; and encodes each of the subpictures.

公开(公告)号：US20230007243A1

公开(公告)日：2023-01-05

申请号：US17943971

申请日：2022-09-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Sughosh Pavan SHASHIDHAR ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/159

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.

公开(公告)号：US20220394303A1

公开(公告)日：2022-12-08

申请号：US17885740

申请日：2022-08-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei SUN ,  Chong Soon LIM ,  Han Boon TEO ,  Jing Ya LI ,  Che Wei KUO ,  Chu Tong WANG ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/70 ,  H04N19/186 ,  H04N19/80 ,  H04N19/132 ,  H04N19/124

Abstract: An encoder: includes circuitry, and memory coupled to the circuitry; stores a first parameter into a bitstream, the first parameter indicating whether a syntax element related to a chroma tool offset is present in the bitstream; when the first parameter indicates that the syntax element is present in the bitstream, (i) stores, in the bitstream, one or more second parameters that are used in deblocking filtering for a chroma sample of a current image, in addition to the syntax element, (ii) performs the deblocking filtering using the one or more second parameters, and (iii) encodes the current image; and when the first parameter indicates that the syntax element is not present in the bitstream, encodes the current image without storing the one or more second parameters into the bitstream.

公开(公告)号：US20220394268A1

公开(公告)日：2022-12-08

申请号：US17886275

申请日：2022-08-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/126 ,  H04N19/30 ,  H04N19/18 ,  H04N19/176

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US20220394267A1

公开(公告)日：2022-12-08

申请号：US17884420

申请日：2022-08-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/126 ,  H04N19/30 ,  H04N19/18 ,  H04N19/176

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US20220385909A1

公开(公告)日：2022-12-01

申请号：US17885425

申请日：2022-08-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/126 ,  H04N19/176 ,  H04N19/60

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US20220337876A1

公开(公告)日：2022-10-20

申请号：US17727299

申请日：2022-04-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Che Wei KUO ,  Chong Soon LIM ,  Chu Tong WANG ,  Han Boon TEO ,  Hai Wei SUN ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.