公开(公告)号：US20240177723A1

公开(公告)日：2024-05-30

申请号：US18283404

申请日：2021-11-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Srikanth NAGISETTY ,  Chong Soon LIM ,  Hiroyuki EHARA ,  Akira HARADA

IPC: G10L19/038

CPC classification number: G10L19/038

Abstract: An encoding apparatus includes: a quantization circuit that generates a quantization parameter including first information related to a codebook of vector quantization and second information related to code vectors included in the codebook; and a control circuit that determines which one of first encoding of the first information for the target sub-vector and second encoding of a second number of bits based on the difference between an allocated number of bits for vector quantization and the number of bits of the quantization parameter is to be executed, in accordance with the number of bits available for encoding sub-vectors including at least a target sub-vector among a plurality of sub-vectors in the vector quantization.

公开(公告)号：US20240163431A1

公开(公告)日：2024-05-16

申请号：US18417952

申请日：2024-01-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US20240089493A1

公开(公告)日：2024-03-14

申请号：US18514809

申请日：2023-11-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI

IPC: H04N19/52 ,  H04N19/12 ,  H04N19/174 ,  H04N19/182

CPC classification number: H04N19/52 ,  H04N19/12 ,  H04N19/174 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: corrects a base motion vector using a correction value for correcting the base motion vector in a predetermined direction; and encodes a current partition to be encoded in an image of a video, using the base motion vector corrected. The correction value is specified by a first parameter and a second parameter, the first parameter indicating a table to be selected from among a plurality of tables each including values, the second parameter indicating one of the values included in the table to be selected indicated by the first parameter. In each of the plurality of tables, a smaller value among the values is assigned a smaller index. Each of the plurality of tables includes a different minimum value among the values.

公开(公告)号：US20240089479A1

公开(公告)日：2024-03-14

申请号：US18510430

申请日：2023-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Han Boon TEO ,  Takahiro NISHI ,  Ryuichi KANOH ,  Tadamasa TOMA

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176

Abstract: An image encoder writes a first parameter and a second parameter to a bitstream, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image encoder executes the first partition mode including: splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and encoding the plurality of sub blocks.

公开(公告)号：US20230396763A1

公开(公告)日：2023-12-07

申请号：US18365054

申请日：2023-08-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Ru Ling LIAO ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/119 ,  H04N19/60 ,  H04N19/50 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/60 ,  H04N19/50 ,  H04N19/176

Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.

公开(公告)号：US20230362368A1

公开(公告)日：2023-11-09

申请号：US18343393

申请日：2023-06-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Ru Ling LIAO ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/50 ,  H04N19/60

CPC classification number: H04N19/119 ,  H04N19/176 ,  H04N19/50 ,  H04N19/60

Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.

公开(公告)号：US20230319300A1

公开(公告)日：2023-10-05

申请号：US18331800

申请日：2023-06-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

Abstract: An image decoder has circuitry coupled to a memory. The circuitry splits a current image block into a plurality of partitions. The circuitry predicts a first motion vector from a set of uni-prediction motion vector candidates for a first partition of the plurality of partitions, and decodes the first partition using the first motion vector.

公开(公告)号：US20230033765A1

公开(公告)日：2023-02-02

申请号：US17962358

申请日：2022-10-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei KUO ,  Chong Soon LIM ,  Han Boon TEO ,  Jing Ya LI ,  Hai Wei SUN ,  Chu Tong WANG ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/117 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/46

Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.

公开(公告)号：US20220385891A1

公开(公告)日：2022-12-01

申请号：US17875965

申请日：2022-07-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Ru Ling LIAO ,  Chong Soon LIM ,  Han Boon TEO ,  Hai Wei SUN ,  Che Wei KUO ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/105 ,  H04N19/136 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52 ,  H04N19/80

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.

公开(公告)号：US20220353542A1

公开(公告)日：2022-11-03

申请号：US17863123

申请日：2022-07-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Che-Wei KUO ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/82 ,  H04N19/119 ,  H04N19/176 ,  H04N19/593

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.