公开(公告)号：US20220248058A1

公开(公告)日：2022-08-04

申请号：US17724298

申请日：2022-04-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Che Wei KUO ,  Chong Soon LIM ,  Chu Tong WANG ,  Han Boon TEO ,  Hai Wei SUN ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US20220248013A1

公开(公告)日：2022-08-04

申请号：US17725106

申请日：2022-04-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/52 ,  H04N19/176 ,  H04N19/137

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US20220247997A1

公开(公告)日：2022-08-04

申请号：US17722901

申请日：2022-04-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/103 ,  H04N19/186 ,  H04N19/60 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: determines whether an image format of a video is a format including a chroma component; when it is determined that the image format is a format including a chroma component, signals a flag indicating whether application of JCCR is allowed or not in a header of a stream, and (i) encodes the video with application of the JCCR allowed, or (ii) encodes the video with application of the JCCR not allowed; and when it is determined that the image format is a format including no chroma component, signals no flag indicating whether application of the JCCR is allowed or not in the header of the stream, and encodes the video with application of the JCCR not allowed.

公开(公告)号：US20220174305A1

公开(公告)日：2022-06-02

申请号：US17673039

申请日：2022-02-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/46 ,  H04N19/44 ,  H04N19/105 ,  H04N19/169 ,  H04N19/172 ,  H04N19/423

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes, per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD.

公开(公告)号：US20220150483A1

公开(公告)日：2022-05-12

申请号：US17582950

申请日：2022-01-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei KUO ,  Chong Soon LIM ,  Jing Ya LI ,  Han Boon TEO ,  Hai Wei SUN ,  Chu Tong WANG ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/82 ,  H04N19/132 ,  H04N19/159 ,  H04N19/186 ,  H04N19/176

Abstract: An encoder includes circuitry which generates a first coefficient value by applying a CCALF process to a first reconstructed image sample of a luma component; generates a second coefficient value by applying an ALF process to a second reconstructed image sample of a chroma component; generates a third coefficient value by adding the first coefficient value to the second coefficient value; and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry writes a first parameter into a sequence parameter set; writes a second parameter into a parameter set of a picture in response to a value of the first parameter being 1; writes a third parameter into a slice header in response to the value of the first parameter being 1; and writes a fourth parameter into a coding tree unit in response to a value of the third parameter being 1.

公开(公告)号：US20220124336A1

公开(公告)日：2022-04-21

申请号：US17564510

申请日：2021-12-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/13 ,  H04N19/70 ,  H04L65/60 ,  H04N19/176 ,  H04N19/184

Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.

公开(公告)号：US20220103838A1

公开(公告)日：2022-03-31

申请号：US17548815

申请日：2021-12-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hideyuki OHGOSE ,  Kiyofumi ABE ,  Hiroshi ARAKAWA ,  Tatsuro JURI ,  Kazuhito KIMURA

IPC: H04N19/176 ,  H04N19/103 ,  H04N19/146 ,  H04N19/436

Abstract: A video image decoding device receives, as the code string to be decoded, a first code string to be decoded including information based on an encoded residual coefficient and header information or a second code string to be decoded including a residual image obtained in encoding the code string to be decoded and header information. The video image decoding device, when the code string to be decoded that is received by the receiver is the first code string to be decoded, adds the residual decoded image and the predictive image to each other to generate and output a reconstructed image and, when the code string to be decoded received by the receiver is the second code string to be decoded, adds a residual image included in the second code string to be decoded and the predictive image to each other to generate and output a reconstructed image.

公开(公告)号：US20220086502A1

公开(公告)日：2022-03-17

申请号：US17535873

申请日：2021-11-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/70 ,  H04N19/463

Abstract: An encoder includes memory and circuitry coupled to the memory. The circuitry stores a total number of temporal sub-layers in a bitstream into either a picture timing supplemental enhancement information (SEI) message or a buffering period SEI message, and encodes the total number of the temporal sub-layers.

公开(公告)号：US20220060729A1

公开(公告)日：2022-02-24

申请号：US17517066

申请日：2021-11-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/44 ,  H04N19/159 ,  H04N19/46 ,  H04N19/172

Abstract: Circuitry of a decoder is configured to decode an image according to a coding structure including an intra random access point (IRAP) picture, leading pictures to be output before the IRAP picture in output order, and trailing pictures to be output after the IRAP picture in the output order. When the image is decoded, the circuitry decodes, according to a flag in a bitstream, at most one trailing picture among the trailing pictures before decoding the leading pictures in decoding order, and decodes the trailing pictures other than the at most one trailing picture after decoding the leading pictures in the decoding order. The flag indicates whether a picture of each of access units in the bitstream is a field picture. The circuitry decodes the at most one trailing picture before decoding the leading pictures in the decoding order when the flag indicates that the picture is a field picture.

公开(公告)号：US20210400258A1

公开(公告)日：2021-12-23

申请号：US17463889

申请日：2021-09-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Han Boon TEO ,  Hai Wei SUN ,  Che Wei KUO ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/52 ,  H04N19/159

Abstract: Provided is an encoder includes: circuitry; and memory coupled to the circuitry, in which in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size.