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45 条记录 (耗时 0.05 秒)

    POLO-LIKE KINASE INHIBITORS
    41.
    发明申请
    POLO-LIKE KINASE INHIBITORS 失效
    POLO-like激素抑制剂

    公开(公告)号：US20100222575A1

    公开(公告)日：2010-09-02

    申请号：US12680142

    申请日：2008-09-25

    申请人： Christopher McBride ,  Nie Zhe

    发明人： Christopher McBride ,  Nie Zhe

    IPC分类号： C07D487/04

    CPC分类号： C07D487/04 ,  C07D487/14 ,  C07D519/00

    摘要： The present invention relates generally to processes of making 4-(9-cyclopentyl-7,7-difluoro-5-methyl-6-oxo-6,7,8,9-tetrahydro-5H-pyrimido[4,5-b][1,4]diazepin-2-ylamino)-3-methoxy-N-(1-methylpiperidin-4-yl)benzamide and Form A of 4-(9-cyclopentyl-7,7-difluoro-5-methyl-6-oxo-6,7,8,9-tetrahydro-5H-pyrimido[4,5-b][1,4]diazepin-2-ylamino)-3-methoxy-N-(1-methylpiperidin-4-yl)benzamide.

    摘要翻译： 本发明一般涉及制备4-（9-环戊基-7,7-二氟-5-甲基-6-氧代-6,7,8,9-四氢-5H-嘧啶并[4,5-b] [1,4]二氮杂-2-基氨基）-3-甲氧基-N-（1-甲基哌啶-4-基）苯甲酰胺和4-（9-环戊基-7,7-二氟-5-甲基-6 - 氧代-6,7,8,9-四氢-5H-嘧啶并[4,5-b] [1,4]二氮杂-2-基氨基）-3-甲氧基-N-（1-甲基哌啶-4-基） 苯甲酰胺。

    Adaptive clock skew in a variably loaded memory bus
    45.
    发明申请
    Adaptive clock skew in a variably loaded memory bus 失效
    可变加载的内存总线中的自适应时钟偏移

    公开(公告)号：US20050182988A1

    公开(公告)日：2005-08-18

    申请号：US11107044

    申请日：2005-04-15

    申请人： Christopher McBride ,  Paul Brownell ,  Timothy McJunkin

    发明人： Christopher McBride ,  Paul Brownell ,  Timothy McJunkin

    IPC分类号： G06F1/10 ,  G06F12/00 ,  G06F1/12

    CPC分类号： G06F1/10

    摘要： The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.

    摘要翻译： 本发明的优选实施例涉及计算机系统内的时钟信号的选择性相位滞后和时间延迟，以补偿由于其开放架构而可能添加到该系统的附加寄生电容。 更具体地，优选实施例涉及时钟信号路径电路，其中每个电路具有不同长度的多个信号路径。 通过允许时钟信号沿特定路径传播，相位滞后或时间延迟被添加到那些时钟信号。 用于时钟信号的特定路径的选择是通过激活电控开关来实现的，该开关本身由计算机系统的上电期间运行的软件程序激活或去激活，所述软件程序确定那些时钟信号作为一个功能的所需相位滞后或时间延迟 的计算机系统中的寄生电容。