-
公开(公告)号：US20220300030A1
公开(公告)日：2022-09-22
申请号：US17715869
申请日：2022-04-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
-
公开(公告)号：US11347608B2
公开(公告)日：2022-05-31
申请号：US16670798
申请日：2019-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/00 , G06F11/20 , G11C11/4093 , G11C29/52
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
-
公开(公告)号：US11341067B2
公开(公告)日：2022-05-24
申请号：US16987472
申请日：2020-08-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Ian Shaeffer
IPC: G06F13/16 , G06F3/06 , G11C11/4076 , G11C11/409 , G11C11/4093
Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
-
公开(公告)号：US11327524B2
公开(公告)日：2022-05-10
申请号：US16707957
申请日：2019-12-09
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
-
公开(公告)号：US20210383857A1
公开(公告)日：2021-12-09
申请号：US17334170
申请日：2021-05-28
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Suresh Rajan , Scott C. Best
IPC: G11C11/408 , G11C5/04 , G11C11/4093 , G06F12/06 , G06F13/16 , G11C7/10
Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
-
Patent Agency Ranking
公开(公告)号：US11069423B2
公开(公告)日：2021-07-20
申请号：US16537021
申请日：2019-08-09
Applicant: Rambus Inc.
Inventor： Scott C. Best , John Eric Linstadt , Paul William Roukema
Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
-
公开(公告)号：US20210133061A1
公开(公告)日：2021-05-06
申请号：US16670798
申请日：2019-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C29/52 , G11C11/4093
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
-
公开(公告)号：US20210043243A1
公开(公告)日：2021-02-11
申请号：US16940858
申请日：2020-07-28
Applicant: Rambus Inc.
Inventor： Scott C. Best
IPC: G11C11/4076 , G06F13/16 , G11C7/22
Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.
-
公开(公告)号：US20210011867A1
公开(公告)日：2021-01-14
申请号：US16987472
申请日：2020-08-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Ian Shaeffer
IPC: G06F13/16 , G06F3/06 , G11C11/4076 , G11C11/409 , G11C11/4093
Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
-
公开(公告)号：US10459660B2
公开(公告)日：2019-10-29
申请号：US15522164
申请日：2015-11-04
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Scott C. Best
Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.
-
-
-
-
-
-
-
-
-
Search Results
184
records
(took 0.12 seconds)
