公开(公告)号：US06434669B1

公开(公告)日：2002-08-13

申请号：US09390189

申请日：1999-09-07

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr.

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr.

IPC: G06F1206

CPC classification number: G06F12/0848 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/121

Abstract: A set associative cache includes a cache controller, a directory, and an array including at least one congruence class containing a plurality of sets. The plurality of sets are partitioned into multiple groups according to which of a plurality of information types each set can store. The sets are partitioned so that at least two of the groups include the same set and at least one of the sets can store fewer than all of the information types. To optimize cache operation, the cache controller dynamically modifies a cache policy of a first group while retaining a cache policy of a second group, thus permitting the operation of the cache to be individually optimized for different information types. The dynamic modification of cache policy can be performed in response to either a hardware-generated or software-generated input.

Abstract translation: 集合关联高速缓存包括高速缓存控制器，目录和包括至少一个包含多个集合的同余类的数组。 多个集合根据每个集合可以存储的多个信息类型中的哪一个被划分为多个组。 这些集合被分区，使得至少两个组包括相同的集合，并且集合中的至少一个可以存储少于所有信息类型的集合。 为了优化高速缓存操作，高速缓存控制器在保留第二组的高速缓存策略的同时动态地修改第一组的高速缓存策略，从而允许高速缓存的操作针对不同的信息类型单独优化。 高速缓存策略的动态修改可以响应于硬件生成的或软件生成的输入来执行。

公开(公告)号：US06389529B1

公开(公告)日：2002-05-14

申请号：US09344059

申请日：1999-06-25

Applicant: Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  Lakshminarayanan Baba Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC: G06F9312

CPC classification number: G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

Abstract: A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates a plurality of architected time dependency fields of a load instruction to create a plurality of dependency fields. The dependency fields holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by one of the dependency fields. The dependency fields are prioritized so that the cycle corresponding to the highest priority field which is available is utilized.

Abstract translation: 用于加载指令的时间执行的系统。 更具体地，该系统实现了由加载指令请求的数据的及时传送。 该系统由处理器，具有对应的L1高速缓存控制器的L1数据高速缓存器和指令处理器组成。 指令处理器操纵加载指令的多个架构时间依赖性字段以创建多个依赖项。 相关性字段保持相对依赖性值，该相关性值用于对L1高速缓存控制器的相对时间排序队列（RTOQ）中的加载指令进行排序。 加载指令在特定时间从RTOQ发送到L1数据高速缓存，以便在由一个依赖项指定的时间内从L1数据高速缓存中加载请求的数据。 优先依赖关系字段，以便利用对应于可用的最高优先级字段的周期。

公开(公告)号：US06370618B1

公开(公告)日：2002-04-09

申请号：US09436376

申请日：1999-11-09

Applicant: Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  James Stephen Fields, Jr.

Inventor： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  James Stephen Fields, Jr.

IPC: G06F1208

CPC classification number: G06F12/0897 ,  G06F12/123

Abstract: A method and system for allocating lower level cache entries for data castout from an upper level cache provides improved computer system performance by adjusting the ordering of least-recently-used (LRU) information within a cache. Data that is castout from a higher level cache can be written after a read is satisfied and the castout entry will not be labeled as most-recently-used. This improves performance under certain operating conditions of a computing system, as castout data is often less important to keep in lower level cache than data that is also present in the higher level cache.

Abstract translation: 通过调整高速缓存中最近最少使用的（LRU）信息的顺序来分配来自上级高速缓存的用于数据丢弃的低级缓存条目的方法和系统提供了改进的计算机系统性能。 在读取满足后，可以写入从较高级缓存中抛出的数据，并且castout条目不会被标记为最近使用的。 这提高了计算系统的某些操作条件下的性能，因为与上级缓存中存在的数据相比，丢弃数据通常对于保持在较低级别的缓存中不太重要。

公开(公告)号：US06360299B1

公开(公告)日：2002-03-19

申请号：US09345644

申请日：1999-06-30

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC: G06F1200

CPC classification number: G06F12/0862 ,  G06F12/121 ,  G06F2212/6028

Abstract: A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.

Abstract translation: 公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。 如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取 值。

公开(公告)号：US06347363B1

公开(公告)日：2002-02-12

申请号：US09024316

申请日：1998-02-17

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC: G06F1208

CPC classification number: G06F12/0811 ,  G06F12/0831 ,  G06F12/123

Abstract: Logically in line caches within a multilevel cache hierarchy are jointly controlled by single cache controller. By combining the cache controller and snoop logic for different levels within the cache hierarchy, separate queues are not required for each level. During a cache access, cache directories are looked up in parallel. Data is retrieved from an upper cache if hit, or from the lower cache if the upper cache misses and the lower cache hits. LRU units may be updated in parallel based on cache directory hits. Alternatively, the lower cache LRU unit may be updated based on cache memory accesses rather than cache directory hits, or the cache hierarchy may be provided with user selectable modes of operation for both LRU unit update schemes. The merged vertical cache controller mechanism does not require the lower cache memory to be inclusive of the upper cache memory. A novel deallocation scheme and update protocol may be implemented in conjunction with the merged vertical cache controller mechanism.

Abstract translation: 逻辑上在多级缓存层次结构中的行高速缓存由单缓存控制器联合控制。 通过将缓存控制器和窥探逻辑组合在缓存层次结构中的不同级别，每个级别不需要单独的队列。 在缓存访问期间，并行查找缓存目录。 如果命中，则从高级缓存中检索数据，如果高速缓存未命中，并且较低级缓存命中，则从较低级缓存中检索数据。 可以基于缓存目录命中并行更新LRU单元。 或者，可以基于高速缓存存储器访问而不是高速缓存目录命中来更新低级缓存LRU单元，或者可以为两个LRU单元更新方案提供用户可选择的操作模式的高速缓存层级。 合并的垂直高速缓存控制器机制不需要较低的高速缓冲存储器来包含高速缓存存储器。 可以结合合并的垂直高速缓存控制器机制来实现新颖的解除分配方案和更新协议。

公开(公告)号：US06345342B1

公开(公告)日：2002-02-05

申请号：US09437177

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F1200

CPC classification number: G06F12/0831

Abstract: A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

Abstract translation: 一种新颖的高速缓存一致性协议提供修改的非请求（Mu）高速缓存状态，以指示保持在高速缓存行中的值已经被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用Mu状态。 读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US06338124B1

公开(公告)日：2002-01-08

申请号：US09368229

申请日：1999-08-04

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

IPC: G06F1208

CPC classification number: G06F12/123 ,  G06F12/0831

Abstract: Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy, with a coherency state and LRU position of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state and LRU position information appended to the combined operation and the snoop responses, whether an update of the LRU position and/or coherency state of a cache line corresponding to the victim within one of the snoopers is required. If so, the combined response logic selects a snooper storage device to have at least the LRU position of a respective cache line corresponding to the victim updated, and appends an update command identifying the selected snooper to the combined response. The snooper selected to be updated may be randomly chosen, selected based on LRU position of the cache line corresponding to the victim within respective storage, or selected based on other criteria.

Abstract translation: 总线的组合响应逻辑接收组合的数据访问，并且通过由存储层级的特定级别中的存储设备发起/撤销分配操作，附加了外推/解除分配的受害者的一致性状态和LRU位置。 总线驱动器侦听器上的侦听器响应于与所附加的受害者对应的本地存储的缓存线的相关性状态和/或LRU位置的组合操作。 组合响应逻辑从相关性状态和附加到组合操作和窥探响应的LRU位置信息中确定与窥探者之一内的受害者对应的高速缓存线的LRU位置和/或一致性状态的更新是否是 需要。 如果是，组合的响应逻辑选择窥探存储设备至少具有与受害者相对应的相应高速缓存行的LRU位置更新，并且将识别所选窥探者的更新命令附加到组合响应。 选择要更新的窥探者可以被随机地选择，基于在相应存储器内对应于受害者的高速缓存线的LRU位置来选择，或者基于其他标准来选择。

公开(公告)号：US06321306B1

公开(公告)日：2001-11-20

申请号：US09437179

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F1212

CPC classification number: G06F12/0831

Abstract: A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

Abstract translation: 一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由 与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。 因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果，可以应用MU状态。 读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。 或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

公开(公告)号：US06321305B1

公开(公告)日：2001-11-20

申请号：US09368230

申请日：1999-08-04

Applicant: Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jody B. Joyner ,  Jerry Don Lewis

IPC: G06F1200

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/0888

Abstract: In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs the storage device initiating the combined operation not to allocate storage for the target of the data access. Instead, the target of the data access may be passed directly to an in-line processor core without storage, may be stored in a horizontal storage device, or may be stored in an in-line, noninclusive, lower level storage device. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.

Abstract translation: 组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的部署时，明确地指示存储设备启动组合操作，而不为数据访问的目标分配存储。 相反，数据访问的目标可以直接传递到没有存储的在线处理器核心，可以被存储在水平存储设备中，或者可以被存储在一个在线的，独立的，低级的存储设备中。 取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。

公开(公告)号：US06292908B1

公开(公告)日：2001-09-18

申请号：US09175391

申请日：1998-10-19

Applicant: Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

IPC: G06F1130

CPC classification number: G06F11/364 ,  G06F11/349

Abstract: An apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit is described. The internal bus operates at a particular frequency, fb. An image of the internal bus is produced, operating at a lower frequency of operations, fo, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be “out-of-phase” with respect to one another. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/aliqn unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, fo. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, fo.

Abstract translation: 描述了用于监视集成电路的内部通信路径即内部总线的装置和方法。 内部总线以特定频率fb运行。 生产内部总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 缓冲器/对准单元处理信号以产生信号的时间延迟版本。 缓冲器/ aliqn单元用于使每个被监控的信号相对于彼此反相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。