公开(公告)号：US5097305A

公开(公告)日：1992-03-17

申请号：US657128

申请日：1991-02-19

申请人： Carver A. Mead ,  Federico Faggin

发明人： Carver A. Mead ,  Federico Faggin

IPC分类号： H01L27/146

CPC分类号： H01L27/14681

摘要： An integrating photosensor includes an NPN phototransistor having its collector connected to a source of positive voltage, a P-channel MOS transistor having its gate connected to row-select line, its source connected to the emitter of the phototransistor, and its drain connected to a column sense line. The NPN phototransistor has an intrinsic base-collector capacitance. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input and a non-inverting input. The non-inverting input is connected to a source of reference voltage the inverting input is connected to a sense line. A P-channel balance transistor is connected between the inverting input and the output of the amplifying element and a capacitor is also connected between the inverting input and output of the amplifying element. An exponential feedback element is connected between the output and the inverting input of the amplifying element. A plurality of integrating photosensors is disposed in an array of rows and columns, with a given row select line connected to the gates of P-channel MOS transistors associated with that given row and a given column sense line connected to the drains of the P-channel MOS transistors associated with that given column.

摘要翻译： 积分光电传感器包括其集电极连接到正电压源的NPN光电晶体管，其栅极连接到行选择线的P沟道MOS晶体管，其源极连接到光电晶体管的发射极，其漏极连接到 列感觉线。 NPN光电晶体管具有本征的基极 - 集电极电容。 根据本发明的积分读出放大器包括具有反相输入和非反相输入的放大元件。 反相输入连接到参考电压源，反相输入连接到感测线。 P沟道平衡晶体管连接在反相输入和放大元件的输出之间，电容器也连接在放大元件的反相输入和输出之间。 指数反馈元件连接在放大元件的输出和反相输入端之间。 多个积分光电传感器被布置成行和列的阵列，其中给定的行选择线连接到与给定行相关联的P沟道MOS晶体管的栅极，以及连接到P沟道的漏极的给定的列感测线， 与给定列相关的通道MOS晶体管。

公开(公告)号：US5095284A

公开(公告)日：1992-03-10

申请号：US580376

申请日：1990-09-10

申请人： Carver A. Mead

发明人： Carver A. Mead

IPC分类号： H03F1/32 ,  H03F3/345 ,  H03F3/45

CPC分类号： H03F3/4508 ,  H03F1/3211 ,  H03F3/345 ,  H03F3/45278 ,  H03F2203/45658 ,  H03F2203/45674

摘要： A first linear voltage to current converter includes an MOS current source transistor with its gate connected to a source of fixed voltage, used to feed the source of an MOS follower transistor. A second linear voltage to current converter includes a bipolar current source transistor with its base connected to a source of fixed voltage, used to feed the source of an MOS follower transistor. A differential pair includes in each leg a bipolar current source transistor with its base connected to a source of fixed voltage feeding the source of an MOS follower transistor. A differential amplifer includes two circuit legs including these transistor circuits.

摘要翻译： 第一线性电压到电流转换器包括MOS电流源晶体管，其栅极连接到固定电压源，用于馈送MOS跟随器晶体管的源极。 第二线性电压到电流转换器包括双极电流源晶体管，其基极连接到固定电压源，用于馈送MOS跟随器晶体管的源极。 差分对包括在每个支路中的双极电流源晶体管，其基极连接到馈送MOS跟随器晶体管的源极的固定电压源。 差分放大器包括包括这些晶体管电路的两个电路支路。

公开(公告)号：US4736333A

公开(公告)日：1988-04-05

申请号：US524545

申请日：1983-08-15

申请人： Carver A. Mead ,  John C. Wawrzynek ,  Tzu-Mu Lin

发明人： Carver A. Mead ,  John C. Wawrzynek ,  Tzu-Mu Lin

IPC分类号： G06F7/544 ,  G06F15/173 ,  G10H7/08 ,  G06F13/00 ,  G06F7/38 ,  G06F7/52 ,  G10H1/00

CPC分类号： G06F15/17375 ,  G06F7/5443 ,  G10H7/08 ,  G06F2207/3884 ,  G10H2250/211

摘要： An array of universal processing elements (UPEs) may be interconnected through a switching matrix in response to control words which are in turn produced by a programmed digital computer in response to commands from a keyboard or a data file, thereby routing the outputs of selected UPEs to other UPEs for further processing and/or combining a sound stream in digital form. The matrix is comprised of both local and global conductors, the local ones being available to selected groups of UPEs. Each UPE is implemented as a digital multiplier, preferably with pipelining, and each UPE is comprised of a plurality of stages, preferably implemented with an adder for computing the sum of a plus the Boolean logic function [b.multidot.m+d.multidot.m] and a multiplexer for forming the function [b.multidot.+d.multidot.m], where a, b, d and m are bits of the respective two's complement number A, B, D and M, whereby the entire array of stages in a UPE computes A+[B.times.M+D.times.(1-M)].

摘要翻译： 可以通过响应于编程数字计算机响应于来自键盘或数据文件的命令的控制字通过开关矩阵来互连通用处理元件（UPE）阵列，从而路由所选择的UPE的输出 到其他UPE，用于进一步处理和/或组合数字形式的声音流。 矩阵由本地和全局导体组成，本地阵列可用于选定的UPE组。 每个UPE被实现为数字乘法器，优选地通过流水线实现，并且每个UPE由多个级组成，优选地用加法器实现，用于计算加上布尔逻辑函数[bxm + dx＆upbar＆m]和多路复用器 用于形成函数[bx + dx＆upbar＆m]，其中a，b，d和m是相应二进制补码A，B，D和M的位，由此UPE中的整个级数阵列计算A + [BxM + Dx（1-M）]。

公开(公告)号：US4716312A

公开(公告)日：1987-12-29

申请号：US47492

申请日：1987-04-27

申请人： Carver A. Mead ,  John C. Wawrzynek

发明人： Carver A. Mead ,  John C. Wawrzynek

IPC分类号： H03K3/356 ,  H03K17/693 ,  H03K19/096 ,  H03K19/21 ,  H03K17/284

CPC分类号： H03K19/215 ,  H03K17/693 ,  H03K19/0963 ,  H03K3/356017 ,  H03K3/356113

摘要： A monodirectional logic form is provided using a bistable circuit of the set-rest type comprised of two cMOS inverters connected in parallel to a source of power (V.sub.dd) by a power-down p-channel MOS transistor. Each of the cMOS inverters is comprised of a first p-channel MOS transistor in source-drain-drain-source series with an n-channel MOS transistor. Two signal-pass n-channel MOS transistors are provided, one a signal-pass transistor connected as a series switch in a first signal (d) line to the input terminal of one cMOS inverter and the output terminal of the other cMOS inverter, and the other a signal-pass transistor connected as a series switch in a second complement signal (d) line to the input terminal of the other cMOS inverter and the output terminal of the one cMOS inverter. The cMOS inverters are thus directly cross-coupled, input to output, and the input to each is gated by one of the pass transistors, while a first phase of a nonoverlapping two-phase clock signal source is applied to the gates of the power-down and signal-pass transistors. A set-reset circuit coupled in series, either directly or by switching functions is connected to receive the second phase clock signal. The signal pass transistors are connected to mutually exclusive switching functions (series-parallel nMOS network) that provide current paths to circuit ground in response to data signals, or circuit paths to the output terminals of another set-reset circuit.

摘要翻译： 使用由通过掉电p沟道MOS晶体管并联连接到功率源（Vdd）的两个cMOS反相器构成的放置型双稳态电路提供单向逻辑形式。 每个cMOS逆变器由源极 - 漏极 - 漏极 - 源极系列中的第一p沟道MOS晶体管与n沟道MOS晶体管组成。 提供两个信号通n沟道MOS晶体管，一个信号通晶体管连接到第一信号（d）中的串联开关到一个cMOS反相器的输入端和另一个cMOS反相器的输出端，以及 另一个作为第二补码信号（d）线路中的串联开关连接到另一个cMOS反相器的输入端子和一个cMOS反相器的输出端子的信号传输晶体管。 因此，cMOS反相器直接交叉耦合，输入到输出，并且每个的输入由通过晶体管中的一个门控，而不重叠的两相时钟信号源的第一相被施加到功率 - 下行和信号传输晶体管。 串联耦合的设置复位电路直接或通过开关功能被连接以接收第二相位时钟信号。 信号传递晶体管连接到相互排斥的开关功能（串联并联nMOS网络），其响应于数据信号或者到另一个设置复位电路的输出端子的电路路径向电路提供电流路径。

公开(公告)号：US06646680B1

公开(公告)日：2003-11-11

申请号：US09164190

申请日：1998-09-30

申请人： Carver A. Mead ,  Richard A. Lyon

发明人： Carver A. Mead ,  Richard A. Lyon

IPC分类号： H04N5235

CPC分类号： H04N5/23293 ,  H04N5/23212

摘要： A focusing method and apparatus, for use with digital cameras having an electronic viewfinder with less display resolution than in the image generated by the camera's photocell array, uses a uniformly subsampled representation of the entire image for focusing, rather than displaying a selected portion of the higher resolution image. The focusing is assisted by the exaggerated discontinuities produced by subsampling. Introducing flicker enhances focusing sensitivity by repetitively displaying, on the electronic viewfinder, a prescribed set of different reduced-resolution images obtained by subsampling the same high-resolution image at different sampling locations. Each subsampled image of the set of reduced resolution images uses a different set of substantially uniformly distributed pixels.

摘要翻译： 用于具有比由照相机的光电池阵列产生的图像更少的显示分辨率的电子取景器的数字照相机的聚焦方法和装置使用整个图像的均匀二次采样表示进行聚焦，而不是显示所选择的部分 更高分辨率的图像。 焦点由辅助采样产生的夸张的不连续性辅助。 引入闪烁通过在电子取景器上重复地显示通过在不同采样位置对相同高分辨率图像进行二次采样而获得的规定的一组不同的缩小分辨率图像来增强聚焦灵敏度。 该组降低分辨率图像的每个子采样图像使用不同的一组基本均匀分布的像素。

公开(公告)号：US06614478B1

公开(公告)日：2003-09-02

申请号：US09302565

申请日：1999-04-30

申请人： Carver A. Mead

发明人： Carver A. Mead

IPC分类号： H04N907

CPC分类号： G02B27/1013 ,  G02B27/1073 ,  G02B27/145 ,  H04N5/2253 ,  H04N9/097

摘要： A method for attaching imagers to color-separation prisms includes the steps of: arranging three solid-state array image sensor integrated circuits behind and in close proximity to the output faces of a color-separating prism having substantially equal optical path lengths for the three paths, the three solid-state array image sensor integrated circuits each having a solid-state array image sensor and bonding pads for electrical connections disposed on a top face thereof; aligning the three sensors such that the images traversing the three paths are coincident within a pixel dimension of the image sensors; filling the space between each output face of the prism and the top face of the corresponding image sensor with index-matched adhesive; and causing the index-matched adhesive to become rigid while maintaining the alignment of the three image sensors.

摘要翻译： 将成像器附着到分色棱镜的方法包括以下步骤：将三个固态阵列图像传感器集成电路布置在具有基本上相同的光路长度的三个路径的分色棱镜的输出面之后并且非常接近 每个具有固态阵列图像传感器的三个固态阵列图像传感器集成电路和设置在其顶面上的用于电连接的接合焊盘; 对准三个传感器，使得穿过三个路径的图像在图像传感器的像素尺寸内重合; 用折射率匹配的粘合剂填充棱镜的每个输出面与相应的图像传感器的顶面之间的空间; 并且使索引匹配的粘合剂变得刚性，同时保持三个图像传感器的对准。

公开(公告)号：US06452835B1

公开(公告)日：2002-09-17

申请号：US09699059

申请日：2000-10-27

申请人： Christopher J. Diorio ,  Carver A. Mead

发明人： Christopher J. Diorio ,  Carver A. Mead

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C16/10

摘要： A pMOS EEPROM cell includes a source, drain, channel, control gate and well contact. The device is a fully functional single element p-type floating gate MOSFET. A floating gate overlaps the well contact and completely surrounds the drain and source implants. The pMOS cell is written to by means of hot-electron injection, using an intrinsic feedback mechanism to write analog values. Hot electrons are generated in the channel by means of hole impact ionization at the transistor's drain. The pMOS cell is erased by Fowler-Nordheim tunneling. The tunneling voltage is applied only to the well to tunnel electrons from the floating gate. The well-source and well-drain junctions are protected from breakdown by means of guard rings.

摘要翻译： pMOS EEPROM单元包括源极，漏极，通道，控制栅极和阱接触。 该器件是一个功能齐全的单元件p型浮栅MOSFET。 浮动栅极与阱接触重叠，并完全围绕漏极和源植入。 通过热电子注入将pMOS单元写入，使用内在反馈机制来写入模拟值。 通过在晶体管漏极处的空穴冲击电离在通道中产生热电子。 Fowler-Nordheim隧道消除了pMOS细胞。 隧道电压仅施加到阱以从浮动栅极隧道电子。 井源井漏井路口通过护环免受破坏。

公开(公告)号：US6088058A

公开(公告)日：2000-07-11

申请号：US865569

申请日：1997-05-29

申请人： Carver A. Mead ,  Tobi Delbruck ,  Min-hwa Chi

发明人： Carver A. Mead ,  Tobi Delbruck ,  Min-hwa Chi

IPC分类号： H04N5/353 ,  H04N5/359 ,  H04N5/369 ,  H04N5/374 ,  H04N3/14 ,  G03B7/00 ,  H04N5/335 ,  H04N9/083

CPC分类号： H04N5/3532 ,  H04N5/353 ,  H04N5/3591 ,  H04N5/3594 ,  H04N5/3741

摘要： An imaging array having overflow protection and electronic shuttering features is realized without an increase in pixel complexity. Overflow protection is provided by pulsing each row of the imager with a small overflow pulse during the sense amplifier reset phase. An electronic shutter is realized using a modified version of the pixel readout timing. The shutter provides sub-frame exposure by restricting the number of line-times a pixel is allowed to integrate. For a full-frame exposure, each pixel is read out once per frame; during readout of the other rows of the array, the pixel integrates. For subframe exposure, the pixel is continually reset, using a shutter pulse applied to the row lines during sense amplifier reset, until a certain number of rows (line-times) before it is to be read out. The pixel then is allowed to integrate until it is read out normally.

摘要翻译： 实现了具有溢出保护和电子快门功能的成像阵列，而不增加像素复杂度。 通过在感测放大器复位阶段期间使成像器的每行脉冲具有小的溢出脉冲来提供溢出保护。 使用像素读出定时的修改版本来实现电子快门。 快门通过限制允许像素集成的行数的次数来提供子帧曝光。 对于全帧曝光，每个像素每帧读出一次; 在读出阵列的其他行期间，像素被整合。 对于子帧曝光，使用在读出放大器复位期间施加到行线的快门脉冲，直到要读出之前的一定数量的行（行时间），像素被连续复位。 然后允许像素整合，直到它被正常读出。

公开(公告)号：US6044162A

公开(公告)日：2000-03-28

申请号：US771704

申请日：1996-12-20

申请人： Carver A. Mead ,  Douglas M. Chabries ,  Keith L. Davis

发明人： Carver A. Mead ,  Douglas M. Chabries ,  Keith L. Davis

IPC分类号： H04R25/00

CPC分类号： H04R25/356 ,  H04R25/505

摘要： A hearing compensation system comprises an input transducer for converting acoustical information at an input thereof to electrical signals at an output thereof, a differential analog-to-digital converter sampling the electrical signals output from the input transducer at an input thereof and outputting differential signal samples at an output thereof, a digital signal processing circuit having an input connected to the output of the differential analog-to-digital converter and operating on the differential signal samples to form processed differential signal samples at an output thereof, and an output transducer for converting electrical signals at an input thereof to acoustical information at an output thereof, the processed differential signal samples coupled to the input of the output transducer.

摘要翻译： 听力补偿系统包括：输入变换器，用于将其输入处的声学信息转换成其输出端的电信号，差分模数转换器对输入的输入端输出的电信号进行采样，并输出差分信号采样 在其输出端具有数字信号处理电路，其输入端连接到差分模数转换器的输出端并对差分信号采样进行操作，以在其输出端形成经处理的差分信号采样，以及输出转换器，用于转换 其输入端的电信号到其输出处的声信息，经处理的差分信号样本耦合到输出换能器的输入端。

公开(公告)号：US5995036A

公开(公告)日：1999-11-30

申请号：US40496

申请日：1998-03-17

申请人： Benjamin E. Nise ,  Carver A. Mead ,  Xialoing Fang

发明人： Benjamin E. Nise ,  Carver A. Mead ,  Xialoing Fang

IPC分类号： H03M3/02 ,  H03M1/12

CPC分类号： H03M3/49

摘要： An analog-to-digital converter comprises a modulator connected to an analog input signal, a decimator connected to the output of the modulator, a normalizer connected to the output of the modulator and forming a digital output signal, and a programmable gain control circuit connected to the output of the normalizer and providing feedback gain control to the modulator and the decimator.

摘要翻译： 模数转换器包括连接到模拟输入信号的调制器，连接到调制器的输出的抽取器，连接到调制器的输出端并形成数字输出信号的标准化器和连接的可编程增益控制电路 到归一化器的输出并且向调制器和抽取器提供反馈增益控制。