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    System and Method for Cache Line Replacement Selection in a Multiprocessor Environment
    41.
    发明申请
    System and Method for Cache Line Replacement Selection in a Multiprocessor Environment 失效
    多处理器环境中缓存线替换选择的系统和方法

    公开(公告)号：US20090164736A1

    公开(公告)日：2009-06-25

    申请号：US11959804

    申请日：2007-12-19

    申请人： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

    发明人： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

    IPC分类号： G06F12/08

    CPC分类号： G06F12/127 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/128

    摘要： A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

    摘要翻译： 用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。 第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。 在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行， 第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

    Barrier and Interrupt Mechanism for High Latency and Out of Order DMA Device
    42.
    发明申请
    Barrier and Interrupt Mechanism for High Latency and Out of Order DMA Device 失效
    高延迟和高阶DMA设备的屏障和中断机制

    公开(公告)号：US20080168191A1

    公开(公告)日：2008-07-10

    申请号：US11621776

    申请日：2007-01-10

    申请人： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

    发明人： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

    IPC分类号： G06F13/28 ,  G06F12/14

    CPC分类号： G06F13/28

    摘要： A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

    摘要翻译： 直接存储器访问（DMA）设备包括屏障和中断机制，允许中断和邮箱操作以确保正确操作的方式发生，但仍然允许在可能的情况下发生高性能无序数据移动。 某些描述符被定义为“屏障描述符”。 当DMA设备遇到屏障描述符时，它确保所有先前的描述符在屏障描述符完成之前完成。 DMA设备进一步确保在与屏障描述符关联的数据移动完成之前，屏障描述符产生的任何中断都不会断言。 DMA控制器仅允许由屏障描述符生成中断。 屏障描述符概念还允许软件将邮箱完成消息嵌入到描述符的分散/收集链接列表中。

    ADDRESS ERROR DETECTION
    44.
    发明申请
    ADDRESS ERROR DETECTION 有权
    地址错误检测

    公开(公告)号：US20130080854A1

    公开(公告)日：2013-03-28

    申请号：US13241598

    申请日：2011-09-23

    申请人： Richard Nicholas

    发明人： Richard Nicholas

    IPC分类号： H03M13/09 ,  G06F11/08

    CPC分类号： G06F11/1076 ,  G06F11/1016 ,  H03M13/05

    摘要： Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.

    摘要翻译： 地址错误检测，包括接收写入数据和写入地址的方法，写入地址对应于存储器中的位置。 基于接收到的写入数据生成纠错码（ECC）位。 基于写入地址和写入数据在计算机上变换写入数据，以产生变换的写入数据。 变换被配置为响应于写入地址或读取地址与从该位置读取的数据之间的不匹配，使得ECC在读取操作期间检测到写入地址的地址错误。 转换的写入数据和ECC位被写入存储器中的位置。

    SYSTEM AND METHOD FOR OPTIMIZING NEIGHBORING CACHE USAGE IN A MULTIPROCESSOR ENVIRONMENT
    45.
    发明申请
    SYSTEM AND METHOD FOR OPTIMIZING NEIGHBORING CACHE USAGE IN A MULTIPROCESSOR ENVIRONMENT 有权
    在多处理器环境中优化相邻高速缓存的系统和方法

    公开(公告)号：US20090164731A1

    公开(公告)日：2009-06-25

    申请号：US11959652

    申请日：2007-12-19

    申请人： Hien Minh Le ,  Jason Alan Cox ,  Robert John Dorsey ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

    发明人： Hien Minh Le ,  Jason Alan Cox ,  Robert John Dorsey ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response. And, in the event the first PU determines to transmit the castout cache line to the second PU, the first PU transmits the castout cache line to the second PU.

    摘要翻译： 用于管理数据的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有包括多个高速缓存行的高速缓存，每个高速缓存行具有多个相关性状态之一，以及 每个PU耦合到多个PU中的至少另一个。 第一PU选择第一PU的第一高速缓存中的多条高速缓存线的转出高速缓存线，以使第一高速缓冲存储器被抛弃。 第一PU向第二PU发送请求，其中第二PU是第一PU的相邻PU，并且该请求包括所选择的丢弃高速缓存行的第一地址和第一相关性状态。 第二PU确定第一地址是否与第二PU中的任何高速缓存行的地址相匹配。 第二PU基于第二高速缓存中的多条高速缓存行中的每一条的一致性状态以及是否存在地址命中，向第一PU发送响应。 第一PU确定是否根据该响应将丢弃高速缓存行发送到第二PU。 并且，在第一PU确定将丢弃高速缓存行发送到第二PU的情况下，第一PU将丢弃高速缓存行发送到第二PU。

    System and Method for Handling E-Mail Attachments in Data Processing Systems
    46.
    发明申请
    System and Method for Handling E-Mail Attachments in Data Processing Systems 审中-公开
    在数据处理系统中处理电子邮件附件的系统和方法

    公开(公告)号：US20090112999A1

    公开(公告)日：2009-04-30

    申请号：US11924643

    申请日：2007-10-26

    申请人： Richard Nicholas

    发明人： Richard Nicholas

    IPC分类号： G06F15/16

    CPC分类号： G06Q10/107

    摘要： A system and method for handling e-mail attachments in a data processing system. A client receives at least one message in a message database stored in a system memory, wherein the at least one message includes at least one attached file. The client displays a main preview of the at least one message, wherein the main preview of the at least one message includes an indicia that represents the at least one attached file. The client expands the main preview of the at least one message into a first sub-preview and a second sub-preview, wherein the first sub-preview represents the at least one message, and wherein the second sub-preview represents the at least one attached file. The client selects the second sub-preview to perform a function on the at least one attached file independent of the at least one message. The client performs the function on the at least one attached file independent of the at least one message.

    摘要翻译： 一种在数据处理系统中处理电子邮件附件的系统和方法。 客户端在存储在系统存储器中的消息数据库中接收至少一个消息，其中至少一个消息包括至少一个附加文件。 客户端显示至少一个消息的主要预览，其中至少一个消息的主要预览包括表示至少一个附加文件的标记。 客户端将至少一个消息的主要预览扩展到第一子预览和第二子预览中，其中第一子预览表示至少一个消息，并且其中第二子预览表示至少一个 附件 客户端选择第二子预览以对该至少一个附加文件执行独立于至少一个消息的功能。 所述客户机独立于所述至少一个消息对所述至少一个附加文件执行所述功能。

    Method and bus prefetching mechanism for implementing enhanced buffer control
    47.
    发明授权
    Method and bus prefetching mechanism for implementing enhanced buffer control 失效
    用于实现增强缓冲区控制的方法和总线预取机制

    公开(公告)号：US07490201B2

    公开(公告)日：2009-02-10

    申请号：US11944644

    申请日：2007-11-26

    申请人： Bernard Charles Drerup ,  Richard Nicholas ,  Barry Joe Wolford

    发明人： Bernard Charles Drerup ,  Richard Nicholas ,  Barry Joe Wolford

    IPC分类号： G06F13/28 ,  G06F12/00

    CPC分类号： G06F13/28

    摘要： A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

    摘要翻译： 提供了一种方法和总线预取机制，用于实现增强的缓冲区控制。 计算机系统包括多个主器件和至少一个从器件通过系统总线交换数据，并且从器件在主器件的控制下预读取数据。 主机产生指示新的或持续请求的继续总线信号。 主机产生一个预取总线信号，指示预取量，包括不预取。 主机包括用于继续读取序列的机制，允许预取，直到作出指示预取量为零的请求。

    Bus arbitration system
    48.
    发明授权
    Bus arbitration system 失效
    总线仲裁系统

    公开(公告)号：US07487276B2

    公开(公告)日：2009-02-03

    申请号：US12048772

    申请日：2008-03-14

    申请人： Richard Nicholas

    发明人： Richard Nicholas

    IPC分类号： G06F13/362

    CPC分类号： G06F13/362

    摘要： A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

    摘要翻译： 用于总线仲裁的电路装置改变设备请求相对于彼此和先前的仲裁序列被仲裁的顺序。 为此，仲裁器根据预定的顺序授予对第一组设备的访问。 仲裁器然后自动改变第二组设备的序列，根据改变的顺序授予对第二组总线的访问。 这些特征允许通过组的仲裁器序列相对于彼此自动变化的顺序，减少锁定的可能性。

    Design Structure for Improved Logic Simulation Using a Negative Unknown Boolean State
    49.
    发明申请
    Design Structure for Improved Logic Simulation Using a Negative Unknown Boolean State 有权
    使用负的未知布尔状态改进逻辑模拟的设计结构

    公开(公告)号：US20080300849A1

    公开(公告)日：2008-12-04

    申请号：US12192309

    申请日：2008-08-15

    申请人： Richard Nicholas

    发明人： Richard Nicholas

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The initialized unknown Boolean states are then fed to one or more simulated logic elements and the simulator simulates the handling of the unknown Boolean state by the simulated logic elements. Examples of simulated logic elements include gates and latches, such as flip-flops, inverters, and basic logic gates. The processing results in at least one negative unknown Boolean state. An example of when a negative unknown Boolean state would result would be when the unknown Boolean state is inverted by an inverter. The resulting negative unknown Boolean state is then fed to other simulated logic elements that generate further simulation results based on processing the negative unknown Boolean state.

    摘要翻译： 提供了一种用于模拟使用未知布尔状态和负未知布尔状态的电路设计的系统和方法。 当模拟电路时，一个或多个初始仿真逻辑元件被初始化为未知布尔状态。 然后将初始化的未知布尔状态馈送到一个或多个仿真逻辑元件，并且模拟器通过模拟逻辑元件模拟未知布尔状态的处理。 模拟逻辑元件的示例包括门和锁存器，例如触发器，反相器和基本逻辑门。 处理结果至少有一个负的未知布尔状态。 当未知的布尔状态由逆变器反相时，将产生负的未知布尔状态的一个例子。 然后将所得到的负未知布尔状态馈送到其他仿真逻辑元件，该逻辑元件基于处理负未知布尔状态生成进一步的仿真结果。

    Descriptor Prefetch Mechanism for High Latency and Out of Order DMA Device
    50.
    发明申请
    Descriptor Prefetch Mechanism for High Latency and Out of Order DMA Device 有权
    高延迟和超出DMA设备的描述符预取机制

    公开(公告)号：US20080168259A1

    公开(公告)日：2008-07-10

    申请号：US11621789

    申请日：2007-01-10

    申请人： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

    发明人： Giora Biran ,  Luis E. De la Torre ,  Bernard C. Drerup ,  Jyoti Gupta ,  Richard Nicholas

    IPC分类号： G06F9/30 ,  G06F12/14 ,  G06F11/00

    CPC分类号： G06F13/28

    摘要： A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.

    摘要翻译： DMA设备将描述符预取到描述符预取缓冲区中。 描述符预取缓冲区的大小在给定的等待时间环境中保存适当数量的描述符。 为了支持描述符的链表，DMA引擎基于它们在存储器中是连续的假设来预取描述符，并丢弃任何被发现违反这个假设的描述符。 DMA引擎寻求通过每个事务请求多个描述符尽可能地保持描述符预取缓冲区已满。 总线引擎从系统内存中读取这些描述符，并将它们写入预取缓冲区。 DMA引擎还可以使用积极的预取，其中总线引擎请求缓冲区将在描述符预取缓冲器中存在任何空间时将支持的最大数量的描述符。 DMA设备丢弃任何其他不能存储的描述符。