公开(公告)号：US20070020849A1

公开(公告)日：2007-01-25

申请号：US11536099

申请日：2006-09-28

申请人： Cheong Hong ,  Gowrishankar Chindalore

发明人： Cheong Hong ,  Gowrishankar Chindalore

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

公开(公告)号：US20070020840A1

公开(公告)日：2007-01-25

申请号：US11188615

申请日：2005-07-25

申请人： Gowrishankar Chindalore

发明人： Gowrishankar Chindalore

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352

摘要： A storage cell includes a semiconductor substrate defining a trench, a bottom dielectric lining the trench, and a charge storage layer on the bottom dielectric. The charge storage layer includes a plurality of discontinuous storage elements (DSEs). A control gate and a top dielectric cover the DSEs. The storage cell includes a source/drain region underlying the trench. The DSEs may be silicon nanocrystals and the control gate may be polysilicon. The control gate may be recessed below an upper surface of the semiconductor substrate and an upper most of the DSEs may be vertically aligned with the control gate upper surface. The storage cell may include an oxide gap structure laterally aligned with the silicon nanocrystals adjacent the trench sidewall and extending vertically from the upper most of the silicon nanocrystals to the upper surface of the substrate. The DSEs include at least programmable two injection regions.

摘要翻译： 存储单元包括限定沟槽的半导体衬底，衬底在沟槽上的底部电介质和底部电介质上的电荷存储层。 电荷存储层包括多个不连续存储元件（DSE）。 一个控制门和一个顶部电介质覆盖了DSE。 存储单元包括在沟槽下面的源极/漏极区域。 DSE可以是硅纳米晶体，并且控制栅极可以是多晶硅。 控制栅极可以在半导体衬底的上表面下方凹入，并且最大的DSE可以与控制栅极上表面垂直对准。 存储单元可以包括与邻近沟槽侧壁的硅纳米晶体横向对齐并从最上面的硅纳米晶体垂直延伸到衬底的上表面的氧化物间隙结构。 DSE至少包括可编程的两个注入区域。

公开(公告)号：US20070004135A1

公开(公告)日：2007-01-04

申请号：US11170444

申请日：2005-06-29

申请人： Gowrishankar Chindalore

发明人： Gowrishankar Chindalore

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L27/112 ,  H01L27/11521 ,  Y10S977/943

摘要： A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16) of the regions of sacrificial material. A discrete charge storage layer (28) overlies the substrate and is between the regions of sacrificial material. In one form a control electrode (34) is formed per memory cell overlying the substrate with an underlying substrate diffusion and laterally adjacent one of the regions of sacrificial material. A third substrate diffusion (60) is positioned between the two control electrodes. In another form two control electrodes are formed per memory cell with a substrate diffusion underlying each control electrode. In both forms a select electrode (64) overlies and is between both of the two control electrodes.

摘要翻译： 存储器电荷存储装置具有覆盖衬底（12）的牺牲材料区域。 对于每个存储器单元，第一掺杂区域（20）和第二掺杂区域（24）形成在衬底内并且在牺牲材料区域中的一个（16）的相对侧上。 离散的电荷存储层（28）覆盖在衬底上并且在牺牲材料的区域之间。 在一种形式中，每个存储单元形成控制电极（34），所述存储单元覆盖在具有下面的衬底扩散并且横向邻近牺牲材料区域之一的衬底上。 第三衬底扩散（60）位于两个控制电极之间。 在另一种形式中，每个存储器单元形成两个控制电极，每个控制电极下面具有衬底扩散。 在这两种形式中，选择电极（64）覆盖并位于两个控制电极之间。

公开(公告)号：US20050013173A1

公开(公告)日：2005-01-20

申请号：US10622353

申请日：2003-07-18

申请人： Erwin Prinz ,  Gowrishankar Chindalore

发明人： Erwin Prinz ,  Gowrishankar Chindalore

IPC分类号： G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/28

CPC分类号： B82Y10/00 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3454 ,  G11C2216/06 ,  H01L21/28273

摘要： A non volatile memory (100) includes an array (102) of transistors (30) having discrete charge storage elements (40). The transistors are programmed by using a two step programming method (60) where a first step (68) is hot carrier injection (HCI) programming with low gate voltages. A second step (78) is selectively utilized on some memory cells to modify the injected charge distribution to enhance the separation of charge distribution between each memory bit within the transistor memory cell. The second step of programming is implemented without adding significant additional time to the programming operation. In one example, the first step injects electrons and the second step injects holes. The resulting distribution of the two steps removes electron charge in the central region of the storage medium.

摘要翻译： 非易失性存储器（100）包括具有离散电荷存储元件（40）的晶体管（30）的阵列（102）。 通过使用两步编程方法（60）对晶体管进行编程，其中第一步骤（68）是具有低栅极电压的热载流子注入（HCI）编程。 选择性地在一些存储器单元上利用第二步骤（78）来修改注入的电荷分布，以增强在晶体管存储单元内的每个存储器位之间的电荷分布的分离。 实现编程的第二步是在不增加编程操作的额外时间的情况下实现。 在一个示例中，第一步骤注入电子，第二步骤注入孔。 所得到的两个步骤的分布在存储介质的中心区域中去除电子电荷。