公开(公告)号：US20070019472A1

公开(公告)日：2007-01-25

申请号：US11188898

申请日：2005-07-25

申请人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

发明人： Jane Yater ,  Gowrishankar Chindalore ,  Cheong Hong

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

摘要翻译： 电子电路可以包括第一存储单元和第二存储单元。 在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。 源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。 在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。 在另一方面，第一和第二存储器单元连接到相同的位线。 当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

公开(公告)号：US20070018232A1

公开(公告)日：2007-01-25

申请号：US11188582

申请日：2005-07-25

申请人： Gowrishankar Chindalore ,  Cheong Hong ,  Craig Swift

发明人： Gowrishankar Chindalore ,  Cheong Hong ,  Craig Swift

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7923

摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

摘要翻译： 存储单元阵列包括限定在半导体衬底中的第一沟槽下面的第一源极/漏极区域和衬底中的第二沟槽下面的第二源极/漏极区域。 电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。 控制门覆盖在第一沟槽上。 控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。 在另一实现中，控制栅极与沟槽平行地延伸。 存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。 扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。 或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。

公开(公告)号：US20060289946A1

公开(公告)日：2006-12-28

申请号：US11165736

申请日：2005-06-24

申请人： Gowrishankar Chindalore

发明人： Gowrishankar Chindalore

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L21/31053 ,  H01L21/76819 ,  H01L27/0203 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.

摘要翻译： 半导体器件包括具有多个非易失性存储单元的存储器阵列。 多个非易失性存储单元中的每个非易失性存储单元具有栅极堆叠。 栅极堆叠包括控制栅极和离散电荷存储层，例如浮动栅极。 在存储器阵列周围形成虚拟堆叠环。 在存储器阵列上形成绝缘层。 虚拟堆叠环的组成和高度与栅堆叠的组成和高度基本相同，以确保绝缘层的CMP在存储器阵列上是均匀的。

公开(公告)号：US20060194438A1

公开(公告)日：2006-08-31

申请号：US10876820

申请日：2004-06-25

申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle ,  Gowrishankar Chindalore

发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle ,  Gowrishankar Chindalore

IPC分类号： H01L21/302 ,  H01L31/112 ,  H01L21/36

CPC分类号： H01L27/11546 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42332

摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.

摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

公开(公告)号：US20060046406A1

公开(公告)日：2006-03-02

申请号：US10930892

申请日：2004-08-31

申请人： Gowrishankar Chindalore ,  James Burnett ,  Craig Swift ,  Ramachandran Muralidhar

发明人： Gowrishankar Chindalore ,  James Burnett ,  Craig Swift ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66833 ,  H01L29/7881

摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.

摘要翻译： 非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。 作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。 这导致通过冲击电离产生电子/空穴对更困难。 因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。 具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。

公开(公告)号：US20050161731A1

公开(公告)日：2005-07-28

申请号：US10765804

申请日：2004-01-27

申请人： Paul Ingersoll ,  Gowrishankar Chindalore ,  Ramachandran Muralidhar

发明人： Paul Ingersoll ,  Gowrishankar Chindalore ,  Ramachandran Muralidhar

IPC分类号： C09K17/14 ,  C09K17/40 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/16 ,  H01L29/423 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4925 ,  H01L29/4958

摘要： To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

摘要翻译： 为了增加半导体器件10的栅极耦合比，离散元件22（例如纳米晶体）沉积在浮置栅极16上。在一个实施例中，分立元件22预先形成为气相并且附着到半导体 装置10通过静电力。 在一个实施例中，分立元件22预先形成在不同于它们附接的腔室的腔室中。 在另一个实施例中，相同的室用于整个沉积工艺。 可选的界面层17可以形成在浮动栅极16和离散元件22之间。

公开(公告)号：US20070177440A1

公开(公告)日：2007-08-02

申请号：US11341809

申请日：2006-01-27

申请人： Craig Swift ,  Gowrishankar Chindalore

发明人： Craig Swift ,  Gowrishankar Chindalore

IPC分类号： G11C29/00

CPC分类号： G11C16/0466 ,  G11C16/12 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.

摘要翻译： 通过将电荷注入存储器单元的电荷存储层来编程存储器单元。 期望的编程电荷导致电荷存储层超过存储器单元的沟道区域的边缘部分。 不期望的编程电荷导致电荷存储层在通道区域的内部部分上。 电荷隧道用于基本上去除电荷存储层中的不期望的编程电荷。 在一种形式中，存储单元具有衬底，其具有沟道区，衬底上的第一介电层和位于第一介电层上的电荷存储层。 电荷存储层上的第二电介质层具有比第二部分厚的第一部分，以选择性地控制电荷隧穿。

公开(公告)号：US20070176226A1

公开(公告)日：2007-08-02

申请号：US11341813

申请日：2006-01-27

申请人： Craig Swift ,  Gowrishankar Chindalore

发明人： Craig Swift ,  Gowrishankar Chindalore

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833

摘要： A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.

摘要翻译： 通过将电荷注入存储器单元的电荷存储层来编程存储器单元。 期望的编程电荷导致电荷存储层超过存储器单元的沟道区域的边缘部分。 不期望的编程电荷导致电荷存储层在通道区域的内部部分上。 电荷隧道用于基本上去除电荷存储层中的不期望的编程电荷。 在一种形式中，存储单元具有衬底，其具有沟道区，衬底上的第一介电层和位于第一介电层上的电荷存储层。 电荷存储层上的第二电介质层具有比第二部分厚的第一部分，以选择性地控制电荷隧穿。

公开(公告)号：US20070117319A1

公开(公告)日：2007-05-24

申请号：US11626681

申请日：2007-01-24

申请人： Gowrishankar Chindalore ,  Craig Swift

发明人： Gowrishankar Chindalore ,  Craig Swift

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。

公开(公告)号：US20070082449A1

公开(公告)日：2007-04-12

申请号：US11556368

申请日：2006-11-03

申请人： Gowrishankar Chindalore

发明人： Gowrishankar Chindalore

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L21/31053 ,  H01L21/76819 ,  H01L27/0203 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.

摘要翻译： 半导体器件包括具有多个非易失性存储单元的存储器阵列。 多个非易失性存储单元中的每个非易失性存储单元具有栅极堆叠。 栅极堆叠包括控制栅极和离散电荷存储层，例如浮动栅极。 在存储器阵列周围形成虚拟堆叠环。 在存储器阵列上形成绝缘层。 虚拟堆叠环的组成和高度与栅堆叠的组成和高度基本相同，以确保绝缘层的CMP在存储器阵列上是均匀的。