公开(公告)号：US08204159B2

公开(公告)日：2012-06-19

申请号：US12094778

申请日：2006-11-25

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H04L27/06

CPC classification number: H04L25/4902 ,  H04L25/38 ,  H04L25/493

Abstract: Circuitry for decoding data from a pulsed signal received on a single line, the circuitry comprising receiving means for receiving a first edge and a second edge on the single line, the first and second edges being separated by a time period, the time period representing said data; decode circuitry comprising determining means arranged to determine a value of the time period and decoding means arranged to decode said data based on said determined value of the time period; a memory arranged to store a reference value; and calibration means for calibrating said decode circuitry based on a comparison between said determined value of the time period and said reference value, wherein the determining means comprises a plurality of sampling units for sampling said pulsed signal at different times, and selection means for selecting the output of one of said sampling units to decoded.

Abstract translation: 用于从在一条线路上接收的脉冲信号中解码数据的电路，所述电路包括接收装置，用于接收单条线路上的第一边缘和第二边缘，所述第一和第二边缘被分隔一段时间段，所述时间段表示所述 数据; 解码电路，包括：确定装置，用于确定所述时间段的值;以及解码装置，被布置为基于所述确定的所述时间段的值来解码所述数据; 布置成存储参考值的存储器; 以及校准装置，用于基于所述确定的时间段值与所述参考值之间的比较校准所述解码电路，其中所述确定装置包括用于在不同时间对所述脉冲信号进行采样的多个采样单元，以及用于选择 输出一个所述采样单元进行解码。

公开(公告)号：US08151151B2

公开(公告)日：2012-04-03

申请号：US12657228

申请日：2010-01-15

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/02 ,  G11C29/00

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US07702974B2

公开(公告)日：2010-04-20

申请号：US11015772

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/26

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US07383481B2

公开(公告)日：2008-06-03

申请号：US11101167

申请日：2005-04-07

Applicant: Robert Warren ,  Robert M. Mills

Inventor： Robert Warren ,  Robert M. Mills

IPC: G01R31/28

CPC classification number: G01R31/318552

Abstract: An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and the test circuitry. The test circuitry is arranged to use the clock signal for testing the functional circuitry.

Abstract translation: 包括功能电路的集成电路; 连接到所述功能电路的测试电路，其中所述测试电路被布置成控制所述功能电路的测试; 以及连接到功能电路和测试电路两者的时钟信号发生电路。 测试电路被设置为使用时钟信号来测试功能电路。

公开(公告)号：US07346822B2

公开(公告)日：2008-03-18

申请号：US11101377

申请日：2005-04-07

Applicant: Robert Warren ,  Robert M. Mills

Inventor： Robert Warren ,  Robert M. Mills

IPC: G01R31/28

CPC classification number: G01R31/318552

Abstract: An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.

Abstract translation: 包括测试电路的集成电路，测试电路包括用于计数时钟信号并具有用于提供控制信号的输出的计数器。 计数器被布置成具有内部状态，并且计数器被布置成在计数器的内部状态上改变控制信号达到预定值。

公开(公告)号：US20070070608A1

公开(公告)日：2007-03-29

申请号：US11242431

申请日：2005-09-29

Applicant: Robert Warren ,  Steve Liang ,  Tony LoBianco ,  Gene Gan

Inventor： Robert Warren ,  Steve Liang ,  Tony LoBianco ,  Gene Gan

IPC: H05K7/00

CPC classification number: H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/30107 ,  H05K1/144 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic module and a process for forming an electronic module are provided. Uniform and sealed air gaps are formed in a vertical direction between two or more electronic devices. The uniform and sealed air gaps are formed by arranging spacers between the electronic devices, where the height of the spacers is selected depending upon the operating characteristics of the particular type of electronic devices.

Abstract translation: 提供了电子模块和用于形成电子模块的工艺。 在两个或更多个电子设备之间沿垂直方向形成均匀和密封的气隙。 均匀和密封的气隙通过在电子设备之间布置间隔件而形成，其中间隔件的高度根据特定类型的电子设备的操作特性来选择。

公开(公告)号：US20050172193A1

公开(公告)日：2005-08-04

申请号：US11015330

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 和（ii）布置成接收测试数据的至少一个测试输入，其中所述测试数据在多个时隙中计时，所述多个部分中的不同部分的测试数据被分配给不同的时隙。

公开(公告)号：US20050165971A1

公开(公告)日：2005-07-28

申请号：US10767505

申请日：2004-01-28

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0661 ,  G06F3/0607 ,  G06F3/0659 ,  G06F3/0674

Abstract: According to one embodiment of the present invention, a data storage device comprises a generic host interface and a media controller. The host interface has a channel select bit encoder to assert one or more channel select bits to be decoded by the media controller to indicate one or more virtual channels through which the host interface will communicate with the media controller over a data bus. A virtual channel controller in the host interface establishes a peer-to-peer connection with a virtual channel controller in the media controller based on the virtual channel indicated by the one or more channel select bits. A communication controller in the host interface implements a communication protocol for communication with a host and transfers data to and from the media controller via the peer-to-peer connection based on the communication with the host.

Abstract translation: 根据本发明的一个实施例，数据存储设备包括通用主机接口和媒体控制器。 主机接口具有信道选择位编码器，用于断言由媒体控制器解码的一个或多个信道选择位，以指示主机接口将通过数据总线与媒体控制器通信的一个或多个虚拟信道。 主机接口中的虚拟通道控制器基于由一个或多个通道选择位指示的虚拟通道建立与媒体控制器中的虚拟通道控制器的对等连接。 主机接口中的通信控制器实现用于与主机通信的通信协议，并且基于与主机的通信，经由对等连接将数据传送到媒体控制器和从媒体控制器传送数据。

公开(公告)号：US20050162768A1

公开(公告)日：2005-07-28

申请号：US10767510

申请日：2004-01-28

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G11B5/09 ,  G11B19/02 ,  G11B20/18 ,  G11B27/034 ,  G11B27/36

CPC classification number: G11B27/034 ,  G11B20/1809 ,  G11B2220/2516

Abstract: A method and system for interleaving storage of data streams on a rotating storage medium of a data storage device comprise dividing the storage medium into a plurality of logical zones. Each logical zone of the plurality of logical zones extends radially from an inner diameter of the storage medium to an outer diameter of the storage medium. Data from a first stream of data is written to a first logical zone of the plurality of logical zones for up to an amount of time corresponding to the rotational speed of the storage medium and the size of the first logical zone.

Abstract translation: 一种用于在数据存储设备的旋转存储介质上交织数据流的存储的方法和系统包括将存储介质分成多个逻辑区。 多个逻辑区域的每个逻辑区域从存储介质的内径径向延伸到存储介质的外径。 来自第一数据流的数据被写入多个逻辑区域的第一逻辑区域，持续时间对应于存储介质的转速和第一逻辑区的大小。

公开(公告)号：US20050078399A1

公开(公告)日：2005-04-14

申请号：US10683973

申请日：2003-10-10

Applicant: Kendall Fung ,  David Dalton ,  Robert Warren

Inventor： Kendall Fung ,  David Dalton ,  Robert Warren

IPC: G11B15/18 ,  G11B20/00 ,  G11B20/10 ,  G11B20/12

CPC classification number: G11B20/1217 ,  G11B20/00007 ,  G11B20/10 ,  G11B2020/1222 ,  G11B2020/1287 ,  G11B2020/1298 ,  G11B2220/2516

Abstract: Method and apparatus for transferring data to and from a data storage medium, such as a rotatable disc in a data storage device. The medium includes a data sector field with a physical length sufficient to store a first data block at a first write frequency. A compression engine compresses the first data block to provide a reduced size, compressed data block. The compressed data block is then written to the data sector field at a second write frequency less than the first write frequency so that the written compressed data block occupies substantially the physical length of said data sector field. This achieves a decreased linear bit density and tends to increase communication channel signal to noise (SNR) ratios and reduce error rates. Data slipping is further advantageously employed so that the first data block further stores at least a portion of a second compressed data block.

Abstract translation: 用于向数据存储介质（例如数据存储设备中的可旋转盘）传送数据和从数据存储介质传送数据的方法和装置。 介质包括具有足以存储第一写入频率的第一数据块的物理长度的数据扇区字段。 压缩引擎压缩第一数据块以提供减小尺寸的压缩数据块。 然后，压缩数据块以小于第一写入频率的第二写入频率被写入数据扇区字段，使得所写入的压缩数据块基本上占据所述数据扇区字段的物理长度。 这实现了线性位密度的降低，并且倾向于增加通信信道信噪比（SNR）比并降低误码率。 更有利地采用数据滑移，使得第一数据块还存储第二压缩数据块的至少一部分。