公开(公告)号：US06744099B2

公开(公告)日：2004-06-01

申请号：US10372329

申请日：2003-02-25

申请人： Ryuta Tsuchiya ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Masatada Horiuchi

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  Y10S257/90

摘要： By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

摘要翻译： 通过抑制MIS场效应晶体管的短沟道效应并减小栅极的边缘电容，可以缩短晶体管中的信号延迟。 通过从具有大介电常数的电介质形成侧壁间隔物形成MIS场效应晶体管，然后在离子注入工艺中将侧壁间隔物用作引入端形成杂质扩散层区域，以引入 杂质。 在这种情况下，具有大介电常数的侧壁隔离物的侧壁具有实现大驱动电流所需的5nm至15nm范围内的最佳膜厚度。 另一方面，外侧的侧壁间隔物由二氧化硅膜构成，该二氧化硅膜是介电常数小的电介质。

公开(公告)号：US06667199B2

公开(公告)日：2003-12-23

申请号：US10081227

申请日：2002-02-25

申请人： Kazuyoshi Torii ,  Ryuta Tsuchiya ,  Masatada Horiuchi ,  Takahiro Onai

发明人： Kazuyoshi Torii ,  Ryuta Tsuchiya ,  Masatada Horiuchi ,  Takahiro Onai

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/82345

摘要： The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a replacement gate type field effect transistor, and the length of the overlap between a gate electrode and a source/drain diffusion zone of the first field effect transistor correspond to that between a gate electrode and a source/drain diffusion zone of the second field effect transistor.

摘要翻译： 本发明提供了具有替代栅电极的MISFET，其确保大的导通电流。一种其中在衬底上形成第一和第二场效应晶体管的半导体器件，第一场效应晶体管是替代栅极型场效应 并且第一场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠的长度对应于第二场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠长度。