公开(公告)号：US07001818B2

公开(公告)日：2006-02-21

申请号：US10825163

申请日：2004-04-16

申请人： Ryuta Tsuchiya ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Masatada Horiuchi

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  Y10S257/90

摘要： By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

公开(公告)号：US20060001111A1

公开(公告)日：2006-01-05

申请号：US11155674

申请日：2005-06-20

申请人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/78696 ,  H01L21/28185 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

摘要： In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n and p types in a complementary MISFET. A gate insulating film for the MISFET is formed as a laminated layer of a metal oxide and an oxynitride. A gate electrode is formed using a polycrystalline Si semiconductor film of the same conductivity type as a source-drain. Predetermined Vth for enhancement are simultaneously achieved by a shift of a flatband voltage produced between the gate insulating film and the gate electrode made of the semiconductor film. Since a variation in Vth due to a statistical fluctuation in the number of impurities with respect to one MISFET can be reduced as compared with the case in which each Vth is controlled by the impurity concentration, Vth and a power supply voltage can both be set low.

摘要翻译： 在完全耗尽的MISFET中，当单晶SOI层变薄到数十nm左右时，在原理上控制阈值电压Vth的限制是有限的。 因此难以在互补的MISFET中同时实现n和p类型的预定Vth。 形成用于MISFET的栅极绝缘膜作为金属氧化物和氧氮化物的叠层。 使用与源极 - 漏极相同的导电类型的多晶硅半导体膜形成栅电极。 用于增强的预定Vth同时通过栅极绝缘膜和由半导体膜制成的栅电极之间产生的平带电压的偏移来实现。 由于相对于一个MISFET而言由于杂质数统计上的波动导致的Vth的变化，与各种Vth被杂质浓度控制的情况相比，可以降低Vth和电源电压两者 。

公开(公告)号：US06744099B2

公开(公告)日：2004-06-01

申请号：US10372329

申请日：2003-02-25

申请人： Ryuta Tsuchiya ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Masatada Horiuchi

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  Y10S257/90

摘要： By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

摘要翻译： 通过抑制MIS场效应晶体管的短沟道效应并减小栅极的边缘电容，可以缩短晶体管中的信号延迟。 通过从具有大介电常数的电介质形成侧壁间隔物形成MIS场效应晶体管，然后在离子注入工艺中将侧壁间隔物用作引入端形成杂质扩散层区域，以引入 杂质。 在这种情况下，具有大介电常数的侧壁隔离物的侧壁具有实现大驱动电流所需的5nm至15nm范围内的最佳膜厚度。 另一方面，外侧的侧壁间隔物由二氧化硅膜构成，该二氧化硅膜是介电常数小的电介质。

公开(公告)号：US06667199B2

公开(公告)日：2003-12-23

申请号：US10081227

申请日：2002-02-25

申请人： Kazuyoshi Torii ,  Ryuta Tsuchiya ,  Masatada Horiuchi ,  Takahiro Onai

发明人： Kazuyoshi Torii ,  Ryuta Tsuchiya ,  Masatada Horiuchi ,  Takahiro Onai

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/82345

摘要： The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a replacement gate type field effect transistor, and the length of the overlap between a gate electrode and a source/drain diffusion zone of the first field effect transistor correspond to that between a gate electrode and a source/drain diffusion zone of the second field effect transistor.

摘要翻译： 本发明提供了具有替代栅电极的MISFET，其确保大的导通电流。一种其中在衬底上形成第一和第二场效应晶体管的半导体器件，第一场效应晶体管是替代栅极型场效应 并且第一场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠的长度对应于第二场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠长度。

公开(公告)号：US09287292B2

公开(公告)日：2016-03-15

申请号：US12277833

申请日：2008-11-25

申请人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

发明人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H03K17/6872

摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

摘要翻译： 提供一种具有薄膜BOX-SOI结构并能够实现逻辑电路的高速操作和存储电路的稳定操作的半导体器件。 根据本发明的半导体器件包括半导体支撑衬底，厚度为10nm的绝缘层和半导体层。 在半导体层的上表面中，形成包括第一栅电极并构成逻辑电路的第一场效晶体管。 此外，在半导体层的上表面中，形成包括第二栅电极并构成存储电路的第二场效应晶体管。 在半导体支撑基板中形成具有不同导电类型的至少三个阱区。 在存在阱区的情况下，第一栅电极下方的半导体支撑衬底的区域和第二栅电极下方的半导体支撑衬底的区域彼此电分离。

公开(公告)号：US07812398B2

公开(公告)日：2010-10-12

申请号：US12400324

申请日：2009-03-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US20100084709A1

公开(公告)日：2010-04-08

申请号：US11993862

申请日：2006-06-30

申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/86

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。 另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。 使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜 并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。 由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。 可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

公开(公告)号：US20080258218A1

公开(公告)日：2008-10-23

申请号：US12105226

申请日：2008-04-17

申请人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/01

CPC分类号： H01L29/045 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.

摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。

公开(公告)号：US07385436B2

公开(公告)日：2008-06-10

申请号：US11714844

申请日：2007-03-07

申请人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

发明人： Kiyoo Itoh ,  Ryuta Tsuchiya ,  Takayuki Kawahara

IPC分类号： H03K3/01

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78648 ,  H03K19/0027 ,  H03K19/00384 ,  H03K19/018585

摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。 在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。 或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。

公开(公告)号：US20070284582A1

公开(公告)日：2007-12-13

申请号：US11746230

申请日：2007-05-09

申请人： SHINICHI SAITO ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： SHINICHI SAITO ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，PMOSFET的驱动电流增加。 在（100）硅衬底上形成具有沿<100>方向的沟道的PMOSFET。 通过STI在垂直于通道的方向上施加压应力。