公开(公告)号：US06667199B2

公开(公告)日：2003-12-23

申请号：US10081227

申请日：2002-02-25

申请人： Kazuyoshi Torii ,  Ryuta Tsuchiya ,  Masatada Horiuchi ,  Takahiro Onai

发明人： Kazuyoshi Torii ,  Ryuta Tsuchiya ,  Masatada Horiuchi ,  Takahiro Onai

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/82345

摘要： The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a replacement gate type field effect transistor, and the length of the overlap between a gate electrode and a source/drain diffusion zone of the first field effect transistor correspond to that between a gate electrode and a source/drain diffusion zone of the second field effect transistor.

摘要翻译： 本发明提供了具有替代栅电极的MISFET，其确保大的导通电流。一种其中在衬底上形成第一和第二场效应晶体管的半导体器件，第一场效应晶体管是替代栅极型场效应 并且第一场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠的长度对应于第二场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠长度。

公开(公告)号：US06313012B1

公开(公告)日：2001-11-06

申请号：US09303080

申请日：1999-04-30

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L2130

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US6004865A

公开(公告)日：1999-12-21

申请号：US612647

申请日：1996-03-08

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/331 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。SOI 通过直接接合技术形成衬底，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US5424575A

公开(公告)日：1995-06-13

申请号：US890787

申请日：1992-06-01

申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/73 ,  H01L29/72

CPC分类号： H01L29/7317 ,  H01L27/1203 ,  H01L29/0692

摘要： A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.

摘要翻译： 半导体器件具有形成在绝缘基板上的电绝缘基板和半导体层。 多个半导体区域被定义为彼此接合以在半导体层中形成至少两个同态。 需要具有小厚度的半导体区域之一的引线导体具有特定结构，使得引线导体与半导体层的主表面处的一个半导体区域接触，以在其间进行电连接，并延伸超过该半导体区域 部分半导体层有助于定义除了前述一个半导体区域以外的半导体区域中的至少一个。

公开(公告)号：US5523602A

公开(公告)日：1996-06-04

申请号：US291652

申请日：1994-08-16

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/304 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US5109263A

公开(公告)日：1992-04-28

申请号：US556365

申请日：1990-07-24

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US5237200A

公开(公告)日：1993-08-17

申请号：US833759

申请日：1992-02-11

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US07001818B2

公开(公告)日：2006-02-21

申请号：US10825163

申请日：2004-04-16

申请人： Ryuta Tsuchiya ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Masatada Horiuchi

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  Y10S257/90

摘要： By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

公开(公告)号：US20060001111A1

公开(公告)日：2006-01-05

申请号：US11155674

申请日：2005-06-20

申请人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Shinichi Sato ,  Masatada Horiuchi

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/78696 ,  H01L21/28185 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

摘要： In a full depletion MISFET, there is a limit to control on a threshold voltage Vth by an impurity concentration in principle when a monocrystalline SOI layer becomes thin on the order of a few tens of nm. It was thus difficult to simultaneously realize predetermined Vth of both n and p types in a complementary MISFET. A gate insulating film for the MISFET is formed as a laminated layer of a metal oxide and an oxynitride. A gate electrode is formed using a polycrystalline Si semiconductor film of the same conductivity type as a source-drain. Predetermined Vth for enhancement are simultaneously achieved by a shift of a flatband voltage produced between the gate insulating film and the gate electrode made of the semiconductor film. Since a variation in Vth due to a statistical fluctuation in the number of impurities with respect to one MISFET can be reduced as compared with the case in which each Vth is controlled by the impurity concentration, Vth and a power supply voltage can both be set low.

摘要翻译： 在完全耗尽的MISFET中，当单晶SOI层变薄到数十nm左右时，在原理上控制阈值电压Vth的限制是有限的。 因此难以在互补的MISFET中同时实现n和p类型的预定Vth。 形成用于MISFET的栅极绝缘膜作为金属氧化物和氧氮化物的叠层。 使用与源极 - 漏极相同的导电类型的多晶硅半导体膜形成栅电极。 用于增强的预定Vth同时通过栅极绝缘膜和由半导体膜制成的栅电极之间产生的平带电压的偏移来实现。 由于相对于一个MISFET而言由于杂质数统计上的波动导致的Vth的变化，与各种Vth被杂质浓度控制的情况相比，可以降低Vth和电源电压两者 。

公开(公告)号：US06744099B2

公开(公告)日：2004-06-01

申请号：US10372329

申请日：2003-02-25

申请人： Ryuta Tsuchiya ,  Masatada Horiuchi

发明人： Ryuta Tsuchiya ,  Masatada Horiuchi

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  Y10S257/90

摘要： By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

摘要翻译： 通过抑制MIS场效应晶体管的短沟道效应并减小栅极的边缘电容，可以缩短晶体管中的信号延迟。 通过从具有大介电常数的电介质形成侧壁间隔物形成MIS场效应晶体管，然后在离子注入工艺中将侧壁间隔物用作引入端形成杂质扩散层区域，以引入 杂质。 在这种情况下，具有大介电常数的侧壁隔离物的侧壁具有实现大驱动电流所需的5nm至15nm范围内的最佳膜厚度。 另一方面，外侧的侧壁间隔物由二氧化硅膜构成，该二氧化硅膜是介电常数小的电介质。