公开(公告)号：US10824499B2

公开(公告)日：2020-11-03

申请号：US15865250

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong Hu ,  Hongzhong Zheng ,  Uksong Kang ,  Zhan Ping

IPC: G06F11/10

Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

公开(公告)号：US10747473B2

公开(公告)日：2020-08-18

申请号：US16149034

申请日：2018-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fred Worley ,  Harry Rogers ,  Gunneswara Marripudi ,  Zhan Ping ,  Vikas Sinha

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40

Abstract: Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

公开(公告)号：US20190294513A1

公开(公告)日：2019-09-26

申请号：US16436087

申请日：2019-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gunneswara R. Marripudi ,  Stephen G. Fischer ,  Zhan Ping ,  Indira Joshi ,  Harry Rogers

IPC: G06F11/20 ,  G06F13/42 ,  G06F13/40

Abstract: A computing system providing high-availability access to computing resources includes: a plurality of interfaces; a plurality of sets of computing resources, each of the sets of computing resources including a plurality of computing resources; and at least three switches, each of the switches being connected to a corresponding one of the interfaces via a host link and being connected to a corresponding one of the sets of computing resources via a plurality of resource connections, each of the switches being configured such that data traffic is distributed to remaining ones of the switches through a plurality of cross-connections between the switches if one of the switches fails.

公开(公告)号：US20190286595A1

公开(公告)日：2019-09-19

申请号：US16433838

申请日：2019-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fred Worley ,  Harry Rogers ,  Sreenivas Krishnan ,  Zhan Ping ,  Michael Scriber

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface

公开(公告)号：US20180260007A1

公开(公告)日：2018-09-13

申请号：US15659538

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhan Ping

IPC: G06F1/20 ,  H05K7/20

Abstract: A storage system with temperature control. The system includes a plurality of storage devices such as solid state drives, a system controller such as a baseboard management controller, and one or more cooling fans. Each storage devices includes a controller configured to estimate the heat load in the storage device and/or an effective temperature, resulting from operations performed in the storage device. The system controller employs active disturbance rejection control to adjust the fan speed based on the estimated heat loads, the estimated temperatures, and/or the sensed internal temperatures, of the storage devices.

公开(公告)号：US09804920B2

公开(公告)日：2017-10-31

申请号：US14720934

申请日：2015-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhan Ping ,  Matteo Monchiero

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/1009 ,  G06F11/16 ,  G11C11/408 ,  G06F11/20

CPC classification number: G06F11/1048 ,  G06F11/1016 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0292 ,  G06F12/0653 ,  G06F12/1009 ,  G06F2201/82 ,  G06F2201/85 ,  G06F2212/1032 ,  G06F2212/65 ,  G06F2212/70 ,  G11C11/408

Abstract: Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

公开(公告)号：US20150134868A1

公开(公告)日：2015-05-14

申请号：US14454309

申请日：2014-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ian P. Shaeffer ,  Zhan Ping

IPC: G06F13/12 ,  G06F15/17 ,  G11C7/10 ,  G06F13/40

CPC classification number: G06F13/126 ,  G06F13/4022 ,  G06F13/4063 ,  G11C7/1075

Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.

Abstract translation: 示例性实施例包括具有被配置为附接到服务器板的多个连接器的插座插入器，所述服务器板包括：具有处理器外形尺寸的第一处理器插座和与第一处理器插槽相关联的第一存储器， 至少第一处理器插槽，所述处理器可访问所述第一存储器，以及具有所述处理器外形尺寸的第二处理器插槽，以及与所述第二处理器插槽相关联的第二存储器，其中所述多个连接器被配置为适合所述处理器外形 ; 以及具有第一模式和第二模式的多模式I / O接口，其中在所述第一模式中提供处理器到处理器通信，并且所述第二模式向第一处理器提供对与第二处理器相关联的第二存储器的可访问性 插座。